JPS6484690A - Printed wiring board and the production thereof - Google Patents

Printed wiring board and the production thereof

Info

Publication number
JPS6484690A
JPS6484690A JP24194487A JP24194487A JPS6484690A JP S6484690 A JPS6484690 A JP S6484690A JP 24194487 A JP24194487 A JP 24194487A JP 24194487 A JP24194487 A JP 24194487A JP S6484690 A JPS6484690 A JP S6484690A
Authority
JP
Japan
Prior art keywords
degradation
layer
conductor
insulating layer
conductor run
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24194487A
Other languages
Japanese (ja)
Other versions
JP2501842B2 (en
Inventor
Junji Kaneko
Yoshiharu Kasai
Kaoru Tone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP62241944A priority Critical patent/JP2501842B2/en
Publication of JPS6484690A publication Critical patent/JPS6484690A/en
Application granted granted Critical
Publication of JP2501842B2 publication Critical patent/JP2501842B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the degradation of the bonding interface between a conductor run and an insulating layer, and to prevent the lowering of the adhesive strength therebetween, by bonding the conductor runs forming a circuit pattern to the insulating layer through an anti-degradation layer of chemically stable material. CONSTITUTION:Conductor runs 4 which form a circuit pattern are bonded to an insulating layer 5, respectively, through an anti-degradation layer 13 of chemically stable material. As a result, when this printed wiring board A is produced or after the production thereof, even if the board A is exposed to the high temperature atmosphere for a long time, the adhesive strength between the anti-degradation layer 13 and the insulating layer 5 can be effectively prevented from being lowered. Moreover, since the degradation of the conductor run 4 is also prevented, the adhesive strength between the conductor run 4 and the anti-degradation layer 13 is correspondingly prevented from being lowered. Now, when the material of the conductor run 4 is copper, the material of the anti-degradation layer 13 employs zinc, nickel, chromium or the like, and when the material of the conductor run 4 is aluminum, then the material of the layer 13 employs aluminum oxide.
JP62241944A 1987-09-26 1987-09-26 Printed wiring board manufacturing method Expired - Lifetime JP2501842B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62241944A JP2501842B2 (en) 1987-09-26 1987-09-26 Printed wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62241944A JP2501842B2 (en) 1987-09-26 1987-09-26 Printed wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JPS6484690A true JPS6484690A (en) 1989-03-29
JP2501842B2 JP2501842B2 (en) 1996-05-29

Family

ID=17081891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62241944A Expired - Lifetime JP2501842B2 (en) 1987-09-26 1987-09-26 Printed wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP2501842B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005172496A (en) * 2003-12-09 2005-06-30 Matsushita Electric Ind Co Ltd Load sensor and its manufacturing method
WO2005053367A3 (en) * 2003-10-30 2005-08-25 Yazaki Europe Ltd Method and apparatus for the manufacture of electric circuits
JP2007103440A (en) * 2005-09-30 2007-04-19 Mitsui Mining & Smelting Co Ltd Wiring board and method of manufacturing the same
JP2010232338A (en) * 2009-03-26 2010-10-14 Kyocera Corp Wiring board and substrate for probe card
JP2013102248A (en) * 2013-03-08 2013-05-23 Shinko Electric Ind Co Ltd Manufacturing method of wiring board and manufacturing method of semiconductor package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687695A (en) * 1979-12-19 1981-07-16 Nippon Mining Co Ltd Copper foil for printed circuit and its manufacture
JPS61183152A (en) * 1985-02-07 1986-08-15 Asahi Glass Co Ltd Glass substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687695A (en) * 1979-12-19 1981-07-16 Nippon Mining Co Ltd Copper foil for printed circuit and its manufacture
JPS61183152A (en) * 1985-02-07 1986-08-15 Asahi Glass Co Ltd Glass substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005053367A3 (en) * 2003-10-30 2005-08-25 Yazaki Europe Ltd Method and apparatus for the manufacture of electric circuits
JP2005172496A (en) * 2003-12-09 2005-06-30 Matsushita Electric Ind Co Ltd Load sensor and its manufacturing method
JP2007103440A (en) * 2005-09-30 2007-04-19 Mitsui Mining & Smelting Co Ltd Wiring board and method of manufacturing the same
JP2010232338A (en) * 2009-03-26 2010-10-14 Kyocera Corp Wiring board and substrate for probe card
JP2013102248A (en) * 2013-03-08 2013-05-23 Shinko Electric Ind Co Ltd Manufacturing method of wiring board and manufacturing method of semiconductor package

Also Published As

Publication number Publication date
JP2501842B2 (en) 1996-05-29

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