JP2013102248A - Manufacturing method of wiring board and manufacturing method of semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board which ensures the adhesion between plating layers regardless of materials forming the plating layers without performing special process when the multiple plating layers are laminated, and to provide a manufacturing method of semiconductor package.SOLUTION: A manufacturing method of a wiring board includes: a pad formation process where a pad, formed by laminating multiple plating layers, is formed on a support medium; an insulation layer formation process where an insulation layer covering the pad is formed on the support medium; a support medium removal process where the support medium is removed to expose a part of the pad from a support medium removal surface of the insulation layer. In the pad formation process, after a surface of one plating layer is roughened, a plating layer, forming a next layer, is laminated on the roughened surface.

Description

  The present invention relates to a method for manufacturing a wiring board having a plating layer and a method for manufacturing a semiconductor package in which a semiconductor chip is mounted on the wiring board.

  FIG. 1 is a cross-sectional view partially illustrating a conventional wiring board. Referring to FIG. 1, a wiring board 100 includes a build-up wiring layer having a first insulating layer 130a, a second insulating layer 130b, a first wiring layer 140a, and a second wiring layer 140b. It is.

  In the wiring substrate 100, a first wiring layer 140a is formed in the lowest layer. A first insulating layer 130a is formed so as to cover the first wiring layer 140a, and a second wiring layer 140b is formed on the first insulating layer 130a. Further, a second insulating layer 130b is formed so as to cover the second wiring layer 140b, and a wiring layer (not shown) and an insulating layer (not shown) are alternately stacked on the second insulating layer 130b. ing. A part of the first wiring layer 140a is exposed from the first insulating layer 130a and functions as an electrode pad connected to the semiconductor chip.

  The first wiring layer 140a and the second wiring layer 140b are electrically connected through a first via hole 130x formed in the first insulating layer 130a. The second wiring layer 140b is electrically connected to the upper wiring layer (not shown) via a second via hole 130y formed in the second insulating layer 130b.

  The first wiring layer 140a has a structure in which a plating layer 150a, a plating layer 150b, and a plating layer 150c are sequentially stacked. The plating layer 150a can be made of, for example, Au, the plating layer 150b can be made of, for example, Ni, and the plating layer 150c can be made of, for example, Cu.

  The first wiring layer 140a can be formed as follows, for example. For example, a support made of a conductor such as Cu is prepared, and a resist film having an opening at the position where the first wiring layer 140a is formed is formed on the support. Then, by an electrolytic plating method using the support as a plating power supply layer, for example, Au constituting the plating layer 150a, Ni constituting the plating layer 150b, etc., Cu constituting the plating layer 150c, etc. sequentially in this order. Laminate. Then, after removing the resist film and forming the first insulating layer 130a and the like, the support is removed (see, for example, Patent Document 1).

JP 2000-323613 A

  By the way, since Ni easily oxidizes, an oxide film that is a non-conductive film may be formed on a part of the surface of Ni. FIG. 2 is an enlarged cross-sectional view illustrating the first wiring layer shown in FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof may be omitted. 2A shows a case where the oxide film 170 is not formed on the surface of the plating layer 150b, and FIG. 2B shows a case where the oxide film 170 is formed on a part of the surface of the plating layer 150b. Show.

  As shown in FIG. 2B, when the oxide film 170 is formed on a part of the surface of the plating layer 150b, the plating layer 150c is laminated on the plating layer 150b with the oxide film 170 interposed therebetween. As a result, it becomes difficult to ensure the adhesion between the plating layer 150b and the plating layer 150c, and the plating layer 150c may be peeled off. Such a problem occurs when Ni, Cr, Fe or a laminate thereof is used as the material of the plating layer 150b.

  In order to avoid the occurrence of such a problem, when the oxide film 170 is formed on a part of the surface of the plating layer 150b, special plating such as strike plating or electrolytic cleaning is performed before the plating layer 150c is stacked. Pretreatment may be performed to remove the oxide film 170. As a result, as shown in FIG. 2A, since the plating layer 150c is laminated on the plating layer 150b without the oxide film 170, the adhesion between the plating layer 150b and the plating layer 150c is ensured. Can do. However, it is preferable not to perform the special pretreatment because it complicates the manufacturing process of the wiring board and the semiconductor package.

  In this way, depending on the material (Ni, Cr, Fe, or a laminate thereof) constituting the plating layer, when a plurality of plating layers are laminated, adhesion between the plating layers is ensured unless special pretreatment is performed. There was a problem that could not be done.

  The present invention has been made in view of the above, and ensures the adhesion between the plating layers without any special treatment when laminating a plurality of plating layers, regardless of the material constituting the plating layers. An object of the present invention is to provide a method for manufacturing a wiring board and a method for manufacturing a semiconductor package.

  The wiring board manufacturing method includes a pad forming step of forming a pad formed by laminating a plurality of plating layers on a support, and an insulating layer forming step of forming an insulating layer covering the pad on the support. And a support removing step of removing the support and exposing a part of the pad from the support removing surface of the insulating layer. In the pad forming step, the surface of a certain plating layer is roughened. After forming the surface, it is a requirement that a next plating layer be laminated on the roughened surface.

  According to the disclosed technology, regardless of the material constituting the plating layer, when stacking a plurality of plating layers, it is possible to ensure the adhesion between the plating layers without performing special treatment. A manufacturing method and a manufacturing method of a semiconductor package can be provided.

It is sectional drawing which partially illustrates the conventional wiring board. FIG. 2 is an enlarged cross-sectional view illustrating a first wiring layer shown in FIG. 1. It is sectional drawing which illustrates the wiring board which has the buildup wiring layer which concerns on the 1st Embodiment of this invention. FIG. 4 is an enlarged cross-sectional view illustrating a first wiring layer shown in FIG. 3. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the wiring board according to the first embodiment of the invention; FIG. 6 is a diagram (part 2) illustrating a manufacturing process of the wiring board according to the first embodiment of the invention; FIG. 6 is a diagram (No. 3) for exemplifying the manufacturing process for the wiring board according to the first embodiment of the invention; FIG. 8 is a diagram (No. 4) for exemplifying the manufacturing process for the wiring board according to the first embodiment of the invention; FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the wiring board according to the first embodiment of the invention; FIG. 6 is a view (No. 6) for exemplifying the manufacturing process for the wiring board according to the first embodiment of the invention; FIG. 10 is a view (No. 7) illustrating the manufacturing step of the wiring board according to the first embodiment of the invention; It is FIG. (The 8) which illustrates the manufacturing process of the wiring board which concerns on the 1st Embodiment of this invention. It is FIG. (The 9) which illustrates the manufacturing process of the wiring board which concerns on the 1st Embodiment of this invention. It is FIG. (10) which illustrates the manufacturing process of the wiring board which concerns on the 1st Embodiment of this invention. It is FIG. (The 11) which illustrates the manufacturing process of the wiring board which concerns on the 1st Embodiment of this invention. It is FIG. (The 12) which illustrates the manufacturing process of the wiring board which concerns on the 1st Embodiment of this invention. It is FIG. (13) which illustrates the manufacturing process of the wiring board which concerns on the 1st Embodiment of this invention. It is an example of the SEM (electron microscope) photograph of the surface of a Ni plating layer. It is a figure which illustrates the relationship between surface roughness Ra of Ni plating layer, and adhesiveness. FIG. 6 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the invention. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on the 2nd Embodiment of this invention. It is FIG. (The 2) which illustrates the manufacturing process of the semiconductor package which concerns on the 2nd Embodiment of this invention.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

<First Embodiment>
[Structure of Wiring Board According to First Embodiment of the Present Invention]
First, the structure of the wiring board according to the first embodiment of the present invention will be described. FIG. 3 is a cross-sectional view illustrating a wiring board having a build-up wiring layer according to the first embodiment of the invention. Referring to FIG. 3, the wiring substrate 10 according to the first embodiment of the present invention includes a first insulating layer 13a, a second insulating layer 13b, a third insulating layer 13c, and a first wiring layer 14a. The wiring board includes a build-up wiring layer having a second wiring layer 14b, a third wiring layer 14c, a fourth wiring layer 14d, and a solder resist layer 16.

  In the wiring substrate 10, a first wiring layer 14a is formed in the lowest layer. A first insulating layer 13a is formed so as to cover the first wiring layer 14a, and a second wiring layer 14b is formed on the first insulating layer 13a. Further, a second insulating layer 13b is formed so as to cover the second wiring layer 14b, and a third wiring layer 14c is formed on the second insulating layer 13b. Further, a third insulating layer 13c is formed so as to cover the third wiring layer 14c, and a fourth wiring layer 14d is formed on the third insulating layer 13c. A part of the first wiring layer 14a is exposed from the first insulating layer 13a and functions as an electrode pad connected to a semiconductor chip or the like.

  The first wiring layer 14a and the second wiring layer 14b are electrically connected through a first via hole 13x formed in the first insulating layer 13a. The second wiring layer 14b and the third wiring layer 14c are electrically connected through a second via hole 13y formed in the second insulating layer 13b. The third wiring layer 14c and the fourth wiring layer 14d are electrically connected through a third via hole 13z formed in the third insulating layer 13c.

  A solder resist layer 16 having an opening 16x is formed so as to cover the fourth wiring layer 14d. The fourth wiring layer 14d exposed in the opening 16x of the solder resist layer 16 functions as an electrode pad connected to a mother board or the like.

4 is an enlarged cross-sectional view illustrating the first wiring layer shown in FIG. 4, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. Referring to FIG. 4, the first wiring layer 14a has a structure in which a plating layer 15a, a plating layer 15b, and a plating layer 15c are sequentially stacked. However, a part of the plating layer 15b of the upper surface 15b ₁ is formed an oxide film 17 is nonconductive film, the plating layer 15b and the plating layer 15c are laminated via the oxide film 17. The oxide film 17 is formed by performing, for example, heat treatment between the formation of the plating layer 15b and the formation of the plating layer 15c.

  The plating layer 15a can be composed of, for example, any one of Au, Ag, Cu, Pd, Sn, or an alloy thereof, or a laminate including two or more of these. The plating layer 15b can be composed of, for example, any one of Ni, Cr, Fe, or an alloy thereof, or a laminate including two or more of these. The plating layer 15c can be made of, for example, Cu.

Upper surface 15b ₁ of the plating layer 15b is roughened, fine irregularities are formed. Surface roughness Ra of the upper surface 15b ₁ of the plating layer 15b, by appropriately adjusting the composition and current density of the plating solution used for forming the plating layer 15b by the electrolytic plating method, is the Ra> 100 nm Yes. Incidentally, the oxide film 17 is therefore, it does not affect the fine irregularities of the upper surface 15b ₁ of the plating layer 15b is a very thin film of about several nm~ several hundred nm, for example.

Thus, easily oxidized such as Ni, the upper surface 15b ₁ of the plating layer 15b which is composed of formed material that easily nonconductive film (such as an oxide film 17) on the surface is roughened, forming fine irregularities As a result, a so-called anchor effect is generated between the plating layer 15 b and the plating layer 15 c laminated via the oxide film 17. As a result, even when the plating layer 15b is made of a material that easily forms the oxide film 17, the adhesion between the plating layer 15b and the plating layer 15c is ensured without removing the oxide film 17 by a special treatment. It is possible to prevent the plating layer 15c from peeling off. Therefore, until forming a plating layer 15c after forming the plating layer 15b, for example, by performing heat treatment or the like, even if the oxide film 17 formed on the upper surface 15b ₁ of the plating layer 15b, a plating layer No peeling of 15c occurs.

[Method of Manufacturing a Wiring Board According to the First Embodiment of the Present Invention]
Next, a method for manufacturing a wiring board according to the first embodiment of the present invention will be described. 5 to 17 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment of the invention. 5 to 17, the same components as those of the wiring board 10 shown in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. A method for manufacturing the wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS.

  First, in the step shown in FIG. 5, the support 11 is prepared. In this embodiment, a copper foil is used as the support 11. The thickness of copper foil can be 35-100 micrometers, for example. In FIG. 5, 11 a indicates the upper surface of the support 11. Next, in the step shown in FIG. 6, a resist film 12 is formed on the upper surface 11 a of the support 11. As the resist film 12, for example, a dry film can be used.

  Next, in a process shown in FIG. 7, a patterning process is performed on the resist film 12 to form an opening 12x in a portion corresponding to the formation position of the first wiring layer 14a. Alternatively, the opening 12x may be formed in advance on the dry film resist film 12, and the resist film 12 having the opening 12x formed thereon may be disposed on the upper surface 11a of the support 11.

  Next, in the process shown in FIG. 8, the plating layer 15a, the plating layer 15b, and the plating layer 15c are formed in the opening 12x of the upper surface 11a of the support 11 by an electrolytic plating method using the support 11 as a plating power feeding layer. The first wiring layer 14a to be formed is formed.

  In order to form the first wiring layer 14a, first, as shown in FIG. 8A, the plating layer 15a is formed in the opening 12x of the upper surface 11a of the support 11. The plating layer 15a can be composed of, for example, any one of Au, Ag, Cu, Pd, Sn, or an alloy thereof, or a laminate including two or more of these. In the case where the plating layer 15a is composed of, for example, a laminate in which Au and Pd are laminated in this order, the thickness of Au is, for example, 0.005 to 0.5 μm, and the thickness of Pd is, for example, 0.005. It can be 0.1 μm.

Subsequently, as shown in FIG. 8B, a plating layer 15b is formed on the plating layer 15a. The plating layer 15b can be composed of, for example, any one of Ni, Cr, Fe, or an alloy thereof, or a laminate including two or more of these. The thickness of the plating layer 15b can be 1-10 micrometers, for example. In forming the plated layer 15b, the surface roughness Ra of the upper surface 15b ₁ of the plating layer 15b is, so that the Ra> 100 nm, it is necessary to appropriately adjust the composition and current density of the plating solution in advance using . However, the upper limit of the surface roughness of the upper surface 15b ₁ of the plating layer 15b is directed to Ra ≦ 1 [mu] m. The upper limit is set when the thickness of the plating layer 15b is, for example, 1 to 10 μm, and the upper limit of the surface roughness of the roughened surface that can be formed is such a value, and more than this. This is because even if the roughened surface is formed, a further effect for improving the adhesion cannot be expected.

For example, when the plating layer 15b is made of Ni, the composition of the plating solution can be, for example, 264 g / l nickel sulfate, 30 g / l boric acid, and 50 g / l nickel chloride. The current density can be, for example 0.3~0.4A / dm ^2. Thus, by appropriately adjusting the composition and current density of the plating solution in advance using the upper surface 15b ₁ of the plating layer 15b is roughened, fine irregularities are formed.

Since the plating layer 15b is made of a material that easily oxidizes and easily forms a nonconductor film on the surface, the plating layer 15b is oxidized after the plating layer 15b is formed, as shown in FIG. 8C. in some cases the oxide film 17 is formed is a non-conductive film on a part of the plating layer 15b of the upper surface 15b _1. Oxide film 17, since for example a very thin film of about several nm~ several hundred nm, does not affect the fine irregularities of the upper surface 15b ₁ of the plating layer 15b.

  Subsequently, as illustrated in FIG. 8D, a plating layer 15 c is formed on the plating layer 15 b via the oxide film 17. The plating layer 15c can be made of, for example, Cu. The thickness of the plating layer 15c can be 5-20 micrometers, for example.

Thus, easily oxidized such as Ni, the upper surface 15b ₁ of the plating layer 15b which is composed of formed material that easily nonconductive film (such as an oxide film 17) on the surface is roughened, forming fine irregularities As a result, a so-called anchor effect is generated between the plating layer 15 b and the plating layer 15 c laminated via the oxide film 17. As a result, even when the plating layer 15b is made of a material that easily forms the oxide film 17, the adhesion between the plating layer 15b and the plating layer 15c is ensured without removing the oxide film 17 by a special treatment. It is possible to prevent the plating layer 15c from peeling off. Therefore, until forming a plating layer 15c after forming the plating layer 15b, for example, by performing heat treatment or the like, even if the oxide film 17 formed on the upper surface 15b ₁ of the plating layer 15b, a plating layer No peeling of 15c occurs.

  Next, in the step shown in FIG. 9, the resist film 12 shown in FIG. 8 is removed. Next, in a step shown in FIG. 10, a first insulating layer 13 a that covers the first wiring layer 14 a is formed on the upper surface 11 a of the support 11. As a material of the first insulating layer 13a, a resin material such as an epoxy resin or a polyimide resin can be used. The first insulating layer 13a can be formed, for example, by laminating a resin film on the support 11 and then pressing (pressing) the resin film, followed by heat treatment at a temperature of about 190 ° C. and curing.

  Next, in a step shown in FIG. 11, the first via hole 13x is formed in the first insulating layer 13a formed on the support 11 by using a laser processing method or the like so that the first wiring layer 14a is exposed. Next, in the step shown in FIG. 12, a seed layer (not shown) is formed on the first insulating layer 13a by an electroless plating method or the like, a resist is applied, the resist is exposed and developed, and thereby the second wiring layer A resist film 18 having an opening 18x corresponding to 14b is formed. As the resist film 18, for example, a photosensitive acrylic resin or the like can be used.

  Next, in the process shown in FIG. 13, the second wiring layer 14b connected to the first wiring layer 14a via the first via hole 13x is connected to the opening 18x by an electrolytic plating method by feeding from a seed layer (not shown). Form. For example, Cu or the like can be used as the second wiring layer 14b. Next, in the step shown in FIG. 14, the second wiring layer 14b is formed by removing the resist film 18 and the seed layer (not shown) shown in FIG.

  Next, in the process shown in FIG. 15, the first wiring layer 14a to the fourth wiring layer 14d and the first insulating layer 13a to the third insulating layer 13c are stacked by repeating the same process as described above. That is, after forming the second insulating layer 13b covering the second wiring layer 14b, the second via hole 13y is formed in the portion of the second insulating layer 13b on the second wiring layer 14b.

  Further, a third wiring layer 14c connected to the second wiring layer 14b through the second via hole 13y is formed on the second insulating layer 13b. For example, Cu or the like can be used as the third wiring layer 14c.

  Further, after forming the third insulating layer 13c covering the third wiring layer 14c, the third via hole 13z is formed in the portion of the third insulating layer 13c on the third wiring layer 14c. Further, a fourth wiring layer 14d connected to the third wiring layer 14c through the third via hole 13z is formed on the third insulating layer 13c. For example, Cu or the like can be used as the fourth wiring layer 14d.

  In this way, a predetermined build-up wiring layer is formed on the upper surface 11a of the support 11. In the present embodiment, four build-up wiring layers (first wiring layer 14a to fourth wiring layer 14d) are formed. However, an n-layer (n is an integer of 1 or more) build-up wiring layers are formed. Also good.

  Next, in a step shown in FIG. 16, a solder resist layer 16 is formed on the third insulating layer 13c so as to cover the fourth wiring layer 14d. As the solder resist layer 16, for example, a photosensitive resin composition containing an epoxy resin, an imide resin, or the like can be used. Next, in the step shown in FIG. 17, the opening 16x is formed by exposing and developing the solder resist layer 16. As a result, the fourth wiring layer 14 d is exposed in the opening 16 x of the solder resist layer 16. On the fourth wiring layer 14d exposed in the opening 16x of the solder resist layer 16, for example, a Ni / Au plating layer in which a Ni plating layer and an Au plating layer are stacked in this order may be provided. The fourth wiring layer 14d exposed in the opening 16x of the solder resist layer 16 functions as an electrode pad connected to a mother board or the like.

  Next, by removing the support 11 shown in FIG. 17, the wiring board 10 according to the first embodiment of the present invention shown in FIG. 3 is manufactured. The support 11 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, since the plating layer 15a is formed on the outermost surface of the first wiring layer 14a, the support 11 can be selectively etched and removed with respect to the first wiring layer 14a. Thereby, a part of the first wiring layer 14a is exposed from the first insulating layer 13a and functions as an electrode pad connected to a semiconductor chip or the like.

[Evaluation of plating layer adhesion]
Then, the result of having evaluated about the adhesiveness of the plating layer manufactured by the manufacturing method which concerns on the 1st Embodiment of this invention is demonstrated. First, a sample for evaluation was prepared. The sample was produced by laminating an Au plating layer, a Pd plating layer, a Ni plating layer, and a Cu plating layer in this order on a Cu plate. In preparing the sample, an oxide film was formed on the surface of the Ni plating layer by heating (180 ° C. × 1 hour), and then a Cu plating layer was formed on the oxide film by a copper sulfate plating method. That is, in each sample, the Cu plating layer is laminated on the Ni plating layer via the oxide film.

  Four types of samples 1 to 4 were produced, samples 1 and 2 were produced by a conventional manufacturing method, and samples 3 and 4 were produced by the method for manufacturing a wiring board according to the first embodiment of the present invention. Three samples 1 to 4 were prepared (referred to as A, B, and C).

  The Cu plates constituting the samples 1 and 2 correspond to the support made of a conductor such as Cu in the above-mentioned “background art”. The Au plating layer and the Pd plating layer (a laminate of Au and Pd) constituting the samples 1 and 2 correspond to the plating layer 150a. The Ni plating layer constituting Samples 1 and 2 corresponds to the plating layer 150b. The Cu plating layer constituting Samples 1 and 2 corresponds to the plating layer 150c.

  The Cu plates constituting the samples 3 and 4 correspond to the support 11 in the “structure of the wiring board according to the first embodiment of the present invention” described above. The Au plating layer and the Pd plating layer (a laminate of Au and Pd) constituting the samples 3 and 4 correspond to the plating layer 15a. The Ni plating layers constituting Samples 3 and 4 correspond to the plating layer 15b. The Cu plating layer constituting Samples 3 and 4 corresponds to the plating layer 15c.

  The thickness of each plating layer in each sample was as shown in Table 1. The composition and current density of the Ni plating solution in each sample were as shown in Table 2.

About samples 1-4, the measurement of the surface roughness Ra of the Ni plating layer by AFM (atomic force microscope) and the adhesion test based on JIS K 5600-5-6 (cross-cut method) were carried out. The results are shown in Table 3, FIG. 18 and FIG. FIG. 18 is an example of an SEM (electron microscope) photograph of the surface of the Ni plating layer. FIG. 19 is a diagram illustrating the relationship between the surface roughness Ra and the adhesion of the Ni plating layer. In FIG. 19, a rectangle A indicates a range of measured data, and a diamond B indicates a range of variation expected from the measured data.

By adjusting the composition and current density of the Ni plating solution as shown in Table 2, the surface roughness Ra of the Ni plating layer can be increased as shown in Table 3 and FIG. Moreover, as shown in Table 3 (adhesion) and FIG. 19, it can be confirmed that the adhesion is improved by increasing the surface roughness Ra of the Ni plating layer. In Table 3, ◯ indicates that no peeling occurred between the Ni plating layer and the Cu plating layer in the test by the cross-cut method, and × indicates between the Ni plating layer and the Cu plating layer in the test by the cross-cut method. It shows that peeling occurred.

  In this experimental result, by setting the surface roughness Ra> 100 [nm] of the Ni plating layer, it is good between the Ni plating layer and the Cu plating layer laminated on the Ni plating layer via the oxide film. Adhesion was obtained. This is because when the fine unevenness formed on the surface of the Ni plating layer is increased to some extent, a so-called anchor effect occurs between the Ni plating layer and the Cu plating layer laminated via an oxide film. Conceivable.

According to the wiring board according to the first embodiment of the present invention, the upper surface of the plating layer 15b made of a material that easily oxidizes Ni or the like and easily forms a nonconductive film (such as the oxide film 17) on the surface. the 15b ₁ roughened by forming fine irregularities, the surface of the oxide film 17 is also fine irregularities is roughened is formed. As a result, a so-called anchor effect occurs between the plating layer 15 b and the plating layer 15 c laminated via the oxide film 17. As a result, even when the plating layer 15 b is made of a material that can easily form the oxide film 17, it is possible to ensure adhesion between the plating layer 15 b and the plating layer 15 c laminated via the oxide film 17. It becomes possible, and peeling of the plating layer 15c can be prevented.

<Second Embodiment>
[Structure of Semiconductor Package According to Second Embodiment of the Present Invention]
In the second embodiment, an example in which the present invention is applied to a semiconductor package provided with a wiring board having a build-up wiring layer will be described. FIG. 20 is a cross-sectional view illustrating a semiconductor package according to the second embodiment of the invention. 20, parts that are the same as the parts shown in FIG. 3 are given the same reference numerals, and explanation thereof is omitted. Referring to FIG. 20, the semiconductor package 20 includes the wiring substrate 10 shown in FIG. 3, a semiconductor chip 21, and an underfill resin 22. A pre-solder 23 is formed on the plating layer 15a constituting the first wiring layer 14a of the wiring board 10 by solder paste application or the like. The plating layer 15a and the pre-solder 23 are electrically connected.

  The semiconductor chip 21 includes a semiconductor integrated circuit (not shown) and an electrode pad (not shown) formed on a thinned semiconductor substrate (not shown) made of silicon or the like, and an electrode pad (not shown). The connection terminal 21a is formed in the above. The connection terminal 21 a of the semiconductor chip 21 is electrically connected to the pre-solder 23. As the connection terminal 21a, a solder ball, Au bump, conductive paste, or the like can be used. When a solder ball is used as the connection terminal 21a, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu, or the like is used as the material of the connection terminal 21a. be able to.

  An underfill resin 22 is filled between the semiconductor chip 21 and the first insulating layer 13a. If the connection terminal 21a of the semiconductor chip 21 is made of solder, the connection terminal 21a and the pre-solder 23 are melted and become an alloy when the semiconductor chip 21 is mounted, and one bump is formed.

[Method for Manufacturing Semiconductor Package According to Second Embodiment of the Present Invention]
Then, the manufacturing method of the semiconductor package concerning the 2nd Embodiment of this invention is demonstrated. 21 to 22 are diagrams illustrating the manufacturing process of the semiconductor package according to the second embodiment of the invention. 21 to 22, the same components as those of the semiconductor package 20 shown in FIG. 20 are denoted by the same reference numerals, and the description thereof may be omitted. A method for manufacturing the semiconductor package 20 according to the second embodiment of the present invention will be described with reference to FIGS.

  First, in the step shown in FIG. 21, the wiring board 10 shown in FIG. 3 is prepared, and the pre-solder 23 is formed on the plating layer 15a constituting the first wiring layer 14a. The pre-solder 23 is obtained by applying a solder paste to the plating layer 15a and performing a reflow process. Further, solder balls may be mounted on the plating layer 15a. Next, in the step shown in FIG. 22, the connection terminals 21 a of the semiconductor chip 21 and the pre-solder 23 formed on the plating layer 15 a of the wiring substrate 10 are electrically connected.

  The electrical connection between the connection terminal 21a of the semiconductor chip 21 and the pre-solder 23 formed on the plating layer 15a of the wiring substrate 10 is performed, for example, by heating to 230 ° C. and melting the solder. In addition, when the connection terminal 21a of the semiconductor chip 21 is made of solder, the connection terminal 21a and the pre-solder 23 are melted to become an alloy, and one bump is formed. Next, an underfill resin 22 is filled between the semiconductor chip 21 and the first insulating layer 13a, thereby completing the semiconductor package 20 shown in FIG.

  According to the semiconductor package 20 according to the second embodiment of the present invention, since the semiconductor package is configured using the wiring substrate 10 according to the first embodiment of the present invention, the first embodiment of the present invention. There is an effect similar to the form.

  The preferred embodiment of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. And substitutions can be added.

  For example, in the second embodiment, the semiconductor chip 21 is mounted on the surface where the plating layer 15a is exposed. However, the semiconductor chip 21 has a first surface on which the solder resist layer 16 is formed. It may be mounted on the four wiring layers 14d. In that case, the plating layer 15a constituting the first wiring layer 14a is electrically connected to a mother board or the like.

DESCRIPTION OF SYMBOLS 10 Wiring board 11 Support body 11a Upper surface of support body 11 Resist film 12x, 16x Opening part 13a 1st insulating layer 13b 2nd insulating layer 13c 3rd insulating layer 13x 1st via hole 13y 2nd via hole 13z 3rd via hole 14a 1st Wiring layer 14b Second wiring layer 14c Third wiring layer 14d Fourth wiring layer 15a, 15b, 15c Plating layer 15b Upper surface of _one plating layer 15b 16 Solder resist layer 17 Oxide film 20 Semiconductor package 21 Semiconductor chip 21a Connection terminal 22 Underfill Resin 23 Presolder

Claims (10)

A pad forming step of forming a pad formed by laminating a plurality of plating layers on a support;
An insulating layer forming step of forming an insulating layer covering the pad on the support;
Removing the support and exposing a part of the pad from the support removal surface of the insulating layer, and
In the pad forming step, after a surface of a certain plating layer is made a roughened surface, a subsequent plating layer is laminated on the roughened surface. A via hole forming step of forming a via hole exposing the pad in the insulating layer;
The method for manufacturing a wiring board according to claim 1, further comprising: forming a wiring layer connected to the pad through the via hole on the insulating layer. The pad forming step includes
Forming a first plating layer exposed from the surface of the insulating layer;
Laminating a second plating layer on the first plating layer;
Laminating a third plating layer on the second plating layer,
3. The method of manufacturing a wiring board according to claim 1, wherein the third plating layer is laminated on the roughened surface after making the surface of the second plated layer a roughened surface. 4.   4. The wiring board according to claim 3, wherein the second plating layer is made of any one of Ni, Cr, Fe, or an alloy thereof, or a laminate including two or more thereof. Production method.   The first plating layer is made of any one of Au, Ag, Cu, Pd, Sn, or an alloy thereof, or a laminate composed of two or more thereof. 4. A method for producing a wiring board according to 4.   The method of manufacturing a wiring board according to claim 3, wherein the third plating layer is made of Cu.   The method for manufacturing a wiring board according to claim 1, wherein a surface roughness Ra of the roughened surface is larger than 100 nm.   8. The method for manufacturing a wiring board according to claim 1, further comprising a step of laminating another insulating layer and a wiring layer in multiple layers on the insulating layer.   9. The method of manufacturing a wiring board according to claim 1, wherein the pad is used for connection with a semiconductor chip or for connection with a mother board.   A method for manufacturing a semiconductor package, comprising a semiconductor chip mounting step for mounting a semiconductor chip on a wiring board manufactured by the manufacturing method according to claim 1.