JPS6483391A - Method for forming conductor pattern of circuit board - Google Patents

Method for forming conductor pattern of circuit board

Info

Publication number
JPS6483391A
JPS6483391A JP62239627A JP23962787A JPS6483391A JP S6483391 A JPS6483391 A JP S6483391A JP 62239627 A JP62239627 A JP 62239627A JP 23962787 A JP23962787 A JP 23962787A JP S6483391 A JPS6483391 A JP S6483391A
Authority
JP
Japan
Prior art keywords
conductor
conductor layer
pattern
conductor pattern
specified value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62239627A
Other languages
Japanese (ja)
Inventor
Takao Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62239627A priority Critical patent/JPS6483391A/en
Publication of JPS6483391A publication Critical patent/JPS6483391A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To compose the circuit pattern of high accuracy and high density by trimming a conductor layer by projecting a laser light on the conductor layer on an insulating board and forming the conductor pattern by the remained conductor layer. CONSTITUTION:The laser beam 3 emitted from a laser light oscillator is focused in the spot of which diameter is <= the specified value on the thin conductor layer 2 formed on the whole face of the above of an insulating board 1. The conductor layer 2 is cut by the laser beam 3 according to the preset pattern, trimming grooves 4A, 4B, 4C, 4D, 4F are formed and the conductor pattern of the conductor gap and conductor width of <= the specified value is obtd. Since the dimension of the conductor pattern can be made less than the specified value by trimming the conductor layer by a laser light and reducing the diameter of the spot of a laser beam the circuit pattern of high accuracy and high density can be constituted.
JP62239627A 1987-09-22 1987-09-22 Method for forming conductor pattern of circuit board Pending JPS6483391A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62239627A JPS6483391A (en) 1987-09-22 1987-09-22 Method for forming conductor pattern of circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62239627A JPS6483391A (en) 1987-09-22 1987-09-22 Method for forming conductor pattern of circuit board

Publications (1)

Publication Number Publication Date
JPS6483391A true JPS6483391A (en) 1989-03-29

Family

ID=17047534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62239627A Pending JPS6483391A (en) 1987-09-22 1987-09-22 Method for forming conductor pattern of circuit board

Country Status (1)

Country Link
JP (1) JPS6483391A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525205A (en) * 1993-08-26 1996-06-11 Polyplastics Co., Ltd. Process for forming circuit with laser
JP2004152750A (en) * 2002-10-10 2004-05-27 Matsushita Electric Works Ltd Soldering terminal and treatment method of surface of soldering terminal
US7080451B2 (en) 2000-10-25 2006-07-25 Japan Aviation Electronics Industry Limited Method for manufacturing an electronic component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5525205A (en) * 1993-08-26 1996-06-11 Polyplastics Co., Ltd. Process for forming circuit with laser
US7080451B2 (en) 2000-10-25 2006-07-25 Japan Aviation Electronics Industry Limited Method for manufacturing an electronic component
JP2004152750A (en) * 2002-10-10 2004-05-27 Matsushita Electric Works Ltd Soldering terminal and treatment method of surface of soldering terminal

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