JPS6482545A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS6482545A
JPS6482545A JP23883387A JP23883387A JPS6482545A JP S6482545 A JPS6482545 A JP S6482545A JP 23883387 A JP23883387 A JP 23883387A JP 23883387 A JP23883387 A JP 23883387A JP S6482545 A JPS6482545 A JP S6482545A
Authority
JP
Japan
Prior art keywords
cells
cell
power line
grounding conductor
feedthrough
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23883387A
Other languages
Japanese (ja)
Other versions
JP2656263B2 (en
Inventor
Tamotsu Hiwatari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62238833A priority Critical patent/JP2656263B2/en
Publication of JPS6482545A publication Critical patent/JPS6482545A/en
Application granted granted Critical
Publication of JP2656263B2 publication Critical patent/JP2656263B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Abstract

PURPOSE:To inhibit the increase of cell line length, and to improve the degree of integration of a chip by using a cell for connecting a power line/a grounding conductor as even a feedthrough cell. CONSTITUTION:Power lines P1 composed of first layer metallic wirings and grounding conductors P2 are fitted into each cell line. Severally one virgin terminal is formed to a four input NAND 7, a three input NOR 8 and a three input NAND 9, and the terminals for the NANDs are connected to p1 in cells 2 for connecting the power line/the grounding conductor and the terminal for the NOR to p2. Since these connections are wired by the first layer metallic wirings on the cells for connecting the power line/the grounding conductor, passing wirings 5 consisting of second layer metallic wirings can be shaped onto said cells, and the cells for connecting the power line/the grounding conductor are also used as feedthrough cells. The generation and insertion of the feedthrough cells corresponding to the cells are unnecessitated, thus inhibiting the length of cell lines.
JP62238833A 1987-09-25 1987-09-25 Semiconductor integrated circuit device Expired - Fee Related JP2656263B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238833A JP2656263B2 (en) 1987-09-25 1987-09-25 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238833A JP2656263B2 (en) 1987-09-25 1987-09-25 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS6482545A true JPS6482545A (en) 1989-03-28
JP2656263B2 JP2656263B2 (en) 1997-09-24

Family

ID=17035951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238833A Expired - Fee Related JP2656263B2 (en) 1987-09-25 1987-09-25 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2656263B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150740A (en) * 1985-12-25 1987-07-04 Hitachi Ltd Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62150740A (en) * 1985-12-25 1987-07-04 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JP2656263B2 (en) 1997-09-24

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees