JPS6482238A - Cache memory controller - Google Patents

Cache memory controller

Info

Publication number
JPS6482238A
JPS6482238A JP62238993A JP23899387A JPS6482238A JP S6482238 A JPS6482238 A JP S6482238A JP 62238993 A JP62238993 A JP 62238993A JP 23899387 A JP23899387 A JP 23899387A JP S6482238 A JPS6482238 A JP S6482238A
Authority
JP
Japan
Prior art keywords
hit
array
data
stored
arrays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62238993A
Other languages
Japanese (ja)
Inventor
Yoichi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62238993A priority Critical patent/JPS6482238A/en
Publication of JPS6482238A publication Critical patent/JPS6482238A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To secure the operation even for the occurrence of single trouble and to take a countermeasure against trouble without causing system down by providing plural dual address arrays or the like in which correspondence information between a data array and a main storage is stored. CONSTITUTION:A copy of a part of data in the main storage is stored in a data array 70, and correspondence information to the array 70 is stored in address arrays 30 and 31. A copy of contents of the array 30 is stored in copy address arrays 40 and 41. Hit detecting circuits 50 and 51 check arrays 30 and 31 and output '1' in case of hit, and hit detecting circuits 60 and 61 check arrays 40 and 41 and output '1' in case of hit. Hit is decided if AND between outputs of circuits 50 and 51 is '1' at the time of accessing the array 70, and hit is decided if OR between outputs of circuits 60 and 61 is '1' at the time of checking the occurrence of disaccord between data in the array 70 and data in the main storage. Thus, operation is secured even for the occurrence of single trouble and a countermeasure against trouble is taken without causing system down.
JP62238993A 1987-09-25 1987-09-25 Cache memory controller Pending JPS6482238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238993A JPS6482238A (en) 1987-09-25 1987-09-25 Cache memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238993A JPS6482238A (en) 1987-09-25 1987-09-25 Cache memory controller

Publications (1)

Publication Number Publication Date
JPS6482238A true JPS6482238A (en) 1989-03-28

Family

ID=17038318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238993A Pending JPS6482238A (en) 1987-09-25 1987-09-25 Cache memory controller

Country Status (1)

Country Link
JP (1) JPS6482238A (en)

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