JPS6481057A - Memory device - Google Patents

Memory device

Info

Publication number
JPS6481057A
JPS6481057A JP23745687A JP23745687A JPS6481057A JP S6481057 A JPS6481057 A JP S6481057A JP 23745687 A JP23745687 A JP 23745687A JP 23745687 A JP23745687 A JP 23745687A JP S6481057 A JPS6481057 A JP S6481057A
Authority
JP
Japan
Prior art keywords
pseudo
runaway
cpu
transmitted via
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23745687A
Other languages
Japanese (ja)
Inventor
Shinpei Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23745687A priority Critical patent/JPS6481057A/en
Publication of JPS6481057A publication Critical patent/JPS6481057A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE:To ensure the sure protection of important data despite the runaway of a microcomputer by using a means which delivers a write permission signal only when a specific address designated by a control part is normal. CONSTITUTION:When a microcomputer CPU 1 has runaway, the pseudo data information is transmitted via a data bus 11. At the same time, the pseudo address information is transmitted via an address bus 13 together with a pseudo write signal caused by the noises, etc. However no command is produced for output of a trigger signal to a monostable multivibrator 9 from the CPU 1 due to the runaway of the CPU 1. Thus an OR circuit 7 can inhibit the transmission of the pseudo write signal.
JP23745687A 1987-09-24 1987-09-24 Memory device Pending JPS6481057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23745687A JPS6481057A (en) 1987-09-24 1987-09-24 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23745687A JPS6481057A (en) 1987-09-24 1987-09-24 Memory device

Publications (1)

Publication Number Publication Date
JPS6481057A true JPS6481057A (en) 1989-03-27

Family

ID=17015612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23745687A Pending JPS6481057A (en) 1987-09-24 1987-09-24 Memory device

Country Status (1)

Country Link
JP (1) JPS6481057A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180054A (en) * 1988-01-11 1989-07-18 Nec Corp Memory contents protecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01180054A (en) * 1988-01-11 1989-07-18 Nec Corp Memory contents protecting circuit

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