JPS6480064A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6480064A
JPS6480064A JP23476987A JP23476987A JPS6480064A JP S6480064 A JPS6480064 A JP S6480064A JP 23476987 A JP23476987 A JP 23476987A JP 23476987 A JP23476987 A JP 23476987A JP S6480064 A JPS6480064 A JP S6480064A
Authority
JP
Japan
Prior art keywords
layer
bipolar transistor
heterojunction bipolar
load
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23476987A
Other languages
Japanese (ja)
Inventor
Yasuhiko Kuriyama
Manabu Ishibe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23476987A priority Critical patent/JPS6480064A/en
Publication of JPS6480064A publication Critical patent/JPS6480064A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To make it possible to simply form a high impedance load by a method wherein an FET, having at least a semiconductor layer of a heterojunction bipolar transistor as a channel, is formed and it is used as a saturated resistor. CONSTITUTION:A heterojunction bipolar transistor is composed of an nGaAs layer 3 as a collector, a p<+> GaAs layer 4 as a base layer, an nAlGaAs layer 5 as an emitter, a base electrode 11, an emitter electrode 12 and a collector electrode 13. Also, a p-channel J-DFET is formed for the purpose of formation of a resistance load of said transistor. The J-DFET is composed of the above- mentioned nAlGaAs 5 and the nGaAs 3 as a gate region, and the n<+>GaAs layer 4 as an active layer. The heterojunction bipolar transistor, in which the saturated resistor is used as a load, is used as an inverter circuit, and a high gain can be obtained easily.
JP23476987A 1987-09-21 1987-09-21 Semiconductor device Pending JPS6480064A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23476987A JPS6480064A (en) 1987-09-21 1987-09-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23476987A JPS6480064A (en) 1987-09-21 1987-09-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6480064A true JPS6480064A (en) 1989-03-24

Family

ID=16976076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23476987A Pending JPS6480064A (en) 1987-09-21 1987-09-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6480064A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077231A (en) * 1991-03-15 1991-12-31 Texas Instruments Incorporated Method to integrate HBTs and FETs

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077231A (en) * 1991-03-15 1991-12-31 Texas Instruments Incorporated Method to integrate HBTs and FETs

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