JPS6480031A - Manufacture of resin sealed semiconductor device - Google Patents

Manufacture of resin sealed semiconductor device

Info

Publication number
JPS6480031A
JPS6480031A JP23790487A JP23790487A JPS6480031A JP S6480031 A JPS6480031 A JP S6480031A JP 23790487 A JP23790487 A JP 23790487A JP 23790487 A JP23790487 A JP 23790487A JP S6480031 A JPS6480031 A JP S6480031A
Authority
JP
Japan
Prior art keywords
semiconductor chip
lead frame
sucking hole
vacuum
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23790487A
Other languages
Japanese (ja)
Inventor
Kazuo Usada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23790487A priority Critical patent/JPS6480031A/en
Publication of JPS6480031A publication Critical patent/JPS6480031A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To manufacture resin sealed semiconductor devices without a chip attachment process by using a lead frame modified in the structure, and providing a vacuum sucking hole in the wire bonding machine to directly suck and fix a semiconductor chip. CONSTITUTION:In a predetermined position of a heater block 5 where a semiconductor chip 3 is to be mounted, a vacuum sucking hole 6 smaller than the semiconductor chip 3 is provided. Since this vacuum, sucking hole 6 is evacuated through an evacuation port 7, the semiconductor chip 3 can directly be fixed onto the heater block 5. And, the electrode of the semiconductor chip 3 and the end part of the inner leads 1b of the lead frame are connected by a gold wire 2. Then, a transfer resin sealing equipment is used to seal with a molding resin the central part of the lead frame on which the semiconductor chip 3 is mounted. Finally, using a continuous lead forming machine, the tie bars 1c are removed to shape the outer leads 1d into a predetermined configuration.
JP23790487A 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device Pending JPS6480031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23790487A JPS6480031A (en) 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23790487A JPS6480031A (en) 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6480031A true JPS6480031A (en) 1989-03-24

Family

ID=17022155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23790487A Pending JPS6480031A (en) 1987-09-21 1987-09-21 Manufacture of resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6480031A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6710464B2 (en) 2001-09-10 2004-03-23 Renesas Technology Corp. Resin mold semiconductor device
US6716667B2 (en) 2001-09-05 2004-04-06 Renesas Technology Corp. Semiconductor device manufacturing method, making negative pressure for fixing a chip on a substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6716667B2 (en) 2001-09-05 2004-04-06 Renesas Technology Corp. Semiconductor device manufacturing method, making negative pressure for fixing a chip on a substrate
US6710464B2 (en) 2001-09-10 2004-03-23 Renesas Technology Corp. Resin mold semiconductor device

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