JPS6478524A - Phase locked oscillator - Google Patents

Phase locked oscillator

Info

Publication number
JPS6478524A
JPS6478524A JP62235753A JP23575387A JPS6478524A JP S6478524 A JPS6478524 A JP S6478524A JP 62235753 A JP62235753 A JP 62235753A JP 23575387 A JP23575387 A JP 23575387A JP S6478524 A JPS6478524 A JP S6478524A
Authority
JP
Japan
Prior art keywords
conversion gain
gain control
response
division ratio
frequency division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62235753A
Other languages
Japanese (ja)
Inventor
Takao Shima
Yoshiaki Kumagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62235753A priority Critical patent/JPS6478524A/en
Publication of JPS6478524A publication Critical patent/JPS6478524A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To make a change in a phase noise uniform by generating a conversion gain control signal sent to a conversion gain control terminal in response to a frequency division ratio control signal and applying the conversion gain control in response to the frequency division ratio. CONSTITUTION:A phase comparator 103 is provided with a conversion gain control terminal to control the conversion gain and a conversion gain control circuit 119 generates a conversion gain control signal sent to the conversion gain control terminal in response to the frequency division ratio control signal to apply the conversion gain control in response to the frequency division ratio. The change in the noise band of the phase locked loop is suppressed to keep the damping constant to a constant value by controlling the conversion gain of the comparator 103 in response to the change of the oscillated frequency in the frequency division ratio of the variable frequency divider 115. Thus, the phase noise spectrum changed in response to the oscillated frequency is made uniform over the entire oscillating frequency of a broad band.
JP62235753A 1987-09-19 1987-09-19 Phase locked oscillator Pending JPS6478524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62235753A JPS6478524A (en) 1987-09-19 1987-09-19 Phase locked oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62235753A JPS6478524A (en) 1987-09-19 1987-09-19 Phase locked oscillator

Publications (1)

Publication Number Publication Date
JPS6478524A true JPS6478524A (en) 1989-03-24

Family

ID=16990721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62235753A Pending JPS6478524A (en) 1987-09-19 1987-09-19 Phase locked oscillator

Country Status (1)

Country Link
JP (1) JPS6478524A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645929A (en) * 1992-04-17 1994-02-18 Hughes Aircraft Co Divider of half of integer and low-noise frequency synthesizer using analog gain compensation
JP2011135381A (en) * 2009-12-24 2011-07-07 Fujitsu Ltd Pll circuit and communication equipment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645929A (en) * 1992-04-17 1994-02-18 Hughes Aircraft Co Divider of half of integer and low-noise frequency synthesizer using analog gain compensation
JP2011135381A (en) * 2009-12-24 2011-07-07 Fujitsu Ltd Pll circuit and communication equipment
US8686797B2 (en) 2009-12-24 2014-04-01 Fujitsu Limited Phase locked loop circuit and communication device

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