JPS6478337A - Control system for main memory access priority order - Google Patents

Control system for main memory access priority order

Info

Publication number
JPS6478337A
JPS6478337A JP23370487A JP23370487A JPS6478337A JP S6478337 A JPS6478337 A JP S6478337A JP 23370487 A JP23370487 A JP 23370487A JP 23370487 A JP23370487 A JP 23370487A JP S6478337 A JPS6478337 A JP S6478337A
Authority
JP
Japan
Prior art keywords
segment
circuit
access port
control system
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23370487A
Other languages
Japanese (ja)
Other versions
JPH0528855B2 (en
Inventor
Nobuo Uchida
Yuji Oinaga
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23370487A priority Critical patent/JPS6478337A/en
Priority to CA000577485A priority patent/CA1310429C/en
Priority to AU22318/88A priority patent/AU592717B2/en
Priority to US07/246,087 priority patent/US5073871A/en
Priority to DE3852261T priority patent/DE3852261T2/en
Priority to ES88402360T priority patent/ES2064364T3/en
Priority to EP88402360A priority patent/EP0309330B1/en
Publication of JPS6478337A publication Critical patent/JPS6478337A/en
Publication of JPH0528855B2 publication Critical patent/JPH0528855B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the delay time in a priority cycle and to decrease the hardware quantity against a control circuit by using a BCOC (bus conflict and other checks) circuit to check whether the lower rank addresses of a segment can be set or not to a latch circuit serving as a 2nd access port. CONSTITUTION:The segment addresses set at a 1st access port 15, i.e., the higher rank address signals A6-A4 are supplied to a BCOC circuit 16 in a first priority cycle. Then the conflicts are checked among the buses corresponding to segments and the buses are selected earlier. Then it is checked whether the addresses A3-A0 included in a segment can be set or not to a latch circuit 12 corresponding to a 2nd access port corresponding to each segment. Thus, it is possible to reduce the delay time in the priority cycle and also to decrease the hardware quantity against a control circuit.
JP23370487A 1987-09-19 1987-09-19 Control system for main memory access priority order Granted JPS6478337A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP23370487A JPS6478337A (en) 1987-09-19 1987-09-19 Control system for main memory access priority order
CA000577485A CA1310429C (en) 1987-09-19 1988-09-15 Access priority control system for main storage for computer
AU22318/88A AU592717B2 (en) 1987-09-19 1988-09-16 Access priority control system for main storage for computer
US07/246,087 US5073871A (en) 1987-09-19 1988-09-19 Main storage access priority control system that checks bus conflict condition and logical storage busy condition at different clock cycles
DE3852261T DE3852261T2 (en) 1987-09-19 1988-09-19 Priority access control system to main memory for computers.
ES88402360T ES2064364T3 (en) 1987-09-19 1988-09-19 ACCESS PRIORITY CONTROL SYSTEM FOR MAIN MEMORY FOR A COMPUTER.
EP88402360A EP0309330B1 (en) 1987-09-19 1988-09-19 Access priority control system for main storage for computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23370487A JPS6478337A (en) 1987-09-19 1987-09-19 Control system for main memory access priority order

Publications (2)

Publication Number Publication Date
JPS6478337A true JPS6478337A (en) 1989-03-23
JPH0528855B2 JPH0528855B2 (en) 1993-04-27

Family

ID=16959240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23370487A Granted JPS6478337A (en) 1987-09-19 1987-09-19 Control system for main memory access priority order

Country Status (1)

Country Link
JP (1) JPS6478337A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439549A (en) * 1977-09-05 1979-03-27 Hitachi Ltd Multiple processor
JPS55118164A (en) * 1979-03-07 1980-09-10 Hitachi Ltd Memory bank control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5439549A (en) * 1977-09-05 1979-03-27 Hitachi Ltd Multiple processor
JPS55118164A (en) * 1979-03-07 1980-09-10 Hitachi Ltd Memory bank control system

Also Published As

Publication number Publication date
JPH0528855B2 (en) 1993-04-27

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees