JPH0528855B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] This method relates to a method of accessing a main memory device in which storage space is hierarchically divided, especially when the system is a multi-system system and continuous data such as vector data is read and written. Regarding a main memory access priority control method that takes advantage of the extremely high probability of existing in the same divided storage space, to alleviate the delay time in the priority cycle and to reduce the amount of hardware for the control circuit. When multiple memory access requests are received from multiple processing units logically connected to the main storage unit (MSU), the main storage unit In a storage control unit (MCU), a first access request port that at least temporarily holds a segment address of the memory access request from each of the processing devices;
a first control means connected to the first access request port for controlling, in a first priority cycle, a contention condition for a destination segment determined by an address of the access request; a second access request port that holds an address at least temporarily; and a second access request port that is connected to the output of the second access request port and that controls race conditions within each segment in a second priority cycle.
and is configured to execute a race condition for the segment and a race condition for the intra-segment in different clock cycles.

[Industrial application field]

The present invention relates to a method of accessing a main memory in which storage space is hierarchically divided, and in particular, in a multi-system system, data that is continuous for reading and writing, such as vector data, exists in the same divided storage space. This paper relates to a main memory access priority control method that takes advantage of the fact that the probability of

[Prior art] With the development of integration technology, vector computers that use multiple high-performance circuits to process operations in parallel or in a pipeline, and can perform vector operations in scientific calculations at high speed, have come into practical use. Summer.

In a vector computer, instructions stored in main memory (MSU) are input to a scalar unit,
When it is a vector instruction, it is executed here,
If it is a vector instruction, it is sent to the vector unit. The vector unit continuously fetches the operand data of each vector instruction from the main memory unit (MSU) via the main memory control unit (MCU) to the load instruction execution pipe,
Vector operations are executed in a parallel pipeline using a multiplication execution pipe and a division execution pipe.

In such a vector computer, the storage space of the MSU is hierarchically divided, and there is a very high probability that consecutive data for reading and writing will exist in the same divided storage space within the MSU.

When access requests are made to read or write data in the MSU from multiple processing units or other external devices to such an MSU, priority is determined for each access request, and each partition If each storage space has a different bus and a different memory bank, it is necessary to control the bus contention of each bus and the busy state of each memory bank. In other words, it is important how to control the main memory access priority, and in particular, how to control the priority and the critical logic path of the control circuit that controls the busy check within a determined period (cycle) of the clock signal. How to shorten it is extremely important.

FIG. 3 is a block diagram of a control circuit according to a conventional main memory access priority control method. for example,
It has two main memory control units ( _{MCU), MCU 0 30} and MCU _{1 31} .
1 is divided into four division units called segments (SEG), and each segment is SEG0, SEG1,
SEG2 and SEG3 are, for example, 16 Logical
It is connected to a memory bank called Storage (LS) (not shown). Each segment is then connected to a corresponding bus (not shown). The latch circuit 35 in FIG. 3 corresponds to each segment, and the latch circuit 35 in FIG.
0 corresponds to each bus, and when the valid signal is latched by the latch circuit 35 via the signal line 351, use of the corresponding bus and the memory bank connected thereto is permitted. In this way, each
The MSU consists of 4 segments and each segment consists of 16 memory banks, so it is connected to 64 memory banks and MSU ₀ 3
0 and MSU ₁ , it has 128 memory banks. Access to each memory bank follows the busy check method; if the memory bank is in a busy state, the read/write operation for that memory bank cannot be executed, but if it is not in a busy state, that is, in a ready state, the operation can be executed. Since 16 memory banks are connected to each segment, if access is requested to two or more memory banks simultaneously on the same bus, it is necessary to select a memory bank that is not busy. Also, since data cannot be loaded on commonly connected buses at the same time,
Bus contention occurs, but in this case it is necessary to select a bus that is not in use.

In the conventional main memory access priority control method,
Bus contention for each bus, busy check for each memory bank, and other contention condition checks are executed simultaneously within the same clock signal cycle, and it is determined in one cycle whether or not to issue an access to the MSU. That is, when a memory access request is received from another external device, the address signal 360 of the access request is set in the latch circuit 36 corresponding to the access port, and then the signal line 361 is set in the next cycle (priority cycle). Bus Conflict Check via Bus Conflict
Check) is applied to the circuit 37, and at the same time the signal line 36
2 to the Logical Storage (LS) Busy Check circuit 38, and at the same time, it is applied to the Other Conflict Check (LS) Busy Check circuit 38 via the signal line 363.
Conflict Check) circuit 39. After that, the output signal 37 from each check circuit 37, 38, 39 is output within the same priority cycle.
0,380,390 is the main priority
Control (Main Priority Control) circuit 4
0, and the resulting signal 351 is set in the latch circuit 35. The address signal set in the access port latch circuit 36 is 7 bits from A6 to A0 and corresponds to one of the 128 banks.
The A6 bit is a signal that can access one MSU ₀ 3
Specify either 0 or MSU ₁ 31, A5,
The two bits in A4 specify the four segments within each MSU. In other words, the upper 3 bits (A6, A5,
A4) checks whether there are 8 bus conflicts corresponding to 8 sectors. The bus conflict check circuit 37 inputs the upper address bits (A6, A5, A4), checks whether it matches the code corresponding to the bus in use, and detects the match signal or mismatch signal. The signal line 3
70 to the main priority control circuit 40. Further, the logical storage busy check circuit 38 inputs all 7 bits of the address signal (A6 to A0), and decodes it to generate 128 decoded signals that are sent to the 128 memories. It is checked whether they match the busy signal indicating the busy state of the bank, and the match signal or mismatch signal is applied to the main priority control circuit 40 via the signal line 380. Similarly,
After inputting and decoding the address signal, the other conflict check circuit 39 also compares each decoded signal with signals corresponding to other conflicts, and sends the match signal or mismatch signal to the main circuit via the signal line 390. - Provided to the priority control circuit 40.

Since there are a plurality of access ports corresponding to the latch circuit 36 corresponding to processing devices or other external devices that access the memory, each of the check circuits 37, 38, and 39 has 10 ports. Latch circuit 3 corresponding to the port
6, 36-B, 36-C, . That is, each check circuit 37, 38, 39
exists depending on the port.

Further, the main priority control circuit 40 includes each of the check circuits 37 and 3.
All signals coming from 8 and 39 are input, and a priority circuit is used to determine the priority within the same priority cycle for bus contention, memory bank busy status, and other conflicts, and multiple accesses A bus that can be used and a memory bank that can be used for a request are selected according to priority.

As described above, in the conventional system, a memory access request from a processing device or other external device is made in a request transfer cycle, and once the requested address is set in the latch circuit 36, all memory access requests are made in the next priority cycle. All conflict checks and all priorities for the access port are determined and the resulting signal is sent to latch circuit 3.
After being set to 5, memory access begins on the next MSU issue cycle.

This conventional method has the advantage of fine-grained control because the busy states of all 128 memory banks and the bus contentions of 8 buses are checked simultaneously within the priority cycle. Not only does the quantity of combinational circuits become large, but also the critical logic paths become long, and when the number of ports is large, the delay time and quantity of hardware become major problems.

For example, the circuit shown in FIG.
This circuit inputs a bit address signal (A6 to A0) and checks whether each of the 128 decoded signals matches the busy signals of the 128 memory banks.

Each gate is composed of emitter coupled logic (ECL), the maximum number of inputs to each gate is 4, and emitter coupled logic (ECL) is used to form OR logic by directly connecting the emitters of each gate. It is assumed that the maximum number of dots is also 4. Seven input signals of OR gates 41 and 42 (ADRS BIT0~
6), all addresses (A6 to A0) are logic 0
(0000000), all signals are logic 0,
Seven input signals of OR gates 46 and 47 (ADRS
BIT0-6) are signals that all become logic 0 when addresses A6-A0 are 1 (0000001). The seven input signals (ADRS BIT0 to 7) of OR gates 49 and 50 are all signals that become logic 0 when addresses A6 to A0 are 2nd address (0000010).
Seven input signals of OR gates 52 and 53 (ADRS
BIT0-7) are signals that all become logic 0 when addresses A6-A0 are address 3 (0000011). Pair of OR circuits (41, 42), (46, 4
7), (49, 50), and (52, 53), there are 128 such pairs, so there are 32 circuits in the front section that are the same as the circuit shown in FIG. 4.

The outputs of the OR gates 41 and 42 become logic 0 when all the input signals (ADRS BIT0 to 6) are logic 0, and are input to the NOR gate 43. Since the busy signal BUSY0 is also input to the NOR gate 43, this busy signal is logic 0, and the output signals of the OR gates 41 and 42 are both logic 0.
At this time, the output of the NOR gate 43 becomes logic 1.
Similarly, the outputs of the OR gates 46 and 47 become logic 0 when all the input signals (ADRS BIT0 to 6) are logic 0, and are input to the NOR gate 48. Since a busy signal called BUSY1 is also input to the NOR gate 48, this busy signal is logic 0 and
When the output signals of the OR gates 46 and 47 are both logic 0, the output of the NOR gate 48 becomes logic 1. Similarly, the outputs of OR gates 49 and 50 become logic 0 when all input signals (ADRS BIT0 to 6) are logic 0, and are input to NOR gate 51. Since the signal BUSY2 is also input to the NOR gate 51, when this busy signal is logic 0 and the output signals of the OR gates 49 and 50 are both logic 0, when the output signals of the NOR gate 51 are both logic 0, , the output of the NOR gate 51 becomes logic 1. Similarly, the outputs of OR gates 52 and 53 become logic 0 when all input signals (ADRS BIT0-6) are logic 0, and are input to NOR gate 54. Since a busy signal called BUSY3 is also input to the NOR gate 54, this busy signal is logic 0 and
When the output signals of the OR gates 52 and 53 are both logic 0, the output of the NOR gate 54 becomes logic 1.

The maximum number of inputs for each OR gate is limited to 4, so when ORing 7 inputs, for example, use 4 inputs for OR gate 41 and 4 inputs for OR gate 42, as in OR gates 41 and 42. I have no choice but to use 3 inputs. Also, when OR logic is formed by emitter dots, the maximum is 4, so the second stage NOR circuits 43, 48, 5
The outputs of 1,54 can form an OR with emitter dots. That is, signal 430
is a signal that becomes logic 1 if at least one of the outputs of the NOR gates 43, 48, 51, and 54 is logic 1, and the result is input to the OR gate 44.

Similarly, the limit on the number of inputs for the OR gate 44 is four, so four signal lines, the same as the signal line 430, are input, and if any one of the input signals is a logic 1, the output is a logic 1. There are four other gate circuits similar to the OR gate 44, and their four outputs form an OR by emitter dots, and the result of the OR logic is input to the OR gate 45. Each input of OR gate 44 is associated with four busy signals, so for four inputs of OR gate 44 there are associated 16 busy signals. Since there are four OR gates like OR gate 44, one input of OR gate 45 is related to 16×4=64 busy signals, so other inputs of OR gate 45 are related to 16×4=64 busy signals.
This will cover 128 busy signals.

In the busy check circuit shown in FIG. 4, NOR gates 43, 48, 51, and 54 operate as matching circuits, and each circuit serves as one of the decoded signals generated by decoding the address signal, and one of the 128 memory banks. Detects a match with the corresponding busy signal. The delay time of the busy check circuit in Figure 4 is 4τ, where τ is the delay time of a unit gate.
This is the gate delay time. Also, the total number of gates is 1
417 per port. If there are 10 ports, the number of gates will be 4170, which is very large.

[Problem that the invention seeks to solve]

In the control circuit according to the conventional main memory access priority control method, bus contention, memory bank busy check, and other contention condition checks are executed in the same cycle, and it is determined whether transmission to the main memory is possible or not in one cycle. had decided. Therefore, busy checks for all memory banks, bus contention checks, etc. must be performed for all access ports within one cycle, resulting in a problem of large delay times and increased hardware requirements. Additionally, when the number of access ports increases due to multiprocessorization, the delay time due to wiring is added, and the delay time of critical logical paths in the priority cycle becomes longer, making it necessary to increase the length of one clock cycle. , there is a danger that it will affect the machine cycle of the entire system.

For example, when the number of ports is 4, even if one cycle of the clock signal takes 14 ns, the delay time of the critical logic path in the priority cycle is 13.5 ns, which is suppressed within one clock cycle. Ta. However, when the number of ports increases to 10 due to multiprocessorization, the delay time becomes 20 ns. Even if advances in ECL gate integration technology can reduce the delay time of the critical logic path to 7 ns, the purpose of this progress in integration technology is to reduce the time per clock cycle of the system. If the time of one clock cycle is 5 ns, the delay time of 7 ns increases the machine cycle of the entire system.

The main memory access priority control method of the present invention is as follows:
In vector computers, we note that there is a very high probability that vector data is stored in the same memory bank, so we separate the bus contention check and the memory bank busy status check into two consecutive cycles. This takes advantage of the fact that the performance does not deteriorate. That is, in the present invention, even if a bus that is accessed and is free is selected first, once a memory bank connected to that bus is accessed, if it is vector data, that memory bank or The probability that other memory banks connected to the selected bus will be subsequently accessed is very high, and the circuit that resolves contention between buses takes advantage of this fact that performance does not degrade even if it is simply a comparison circuit. ing. The check circuit that executes the memory bank busy check is a simple circuit that decodes the lower 4 bits of A3 to A0 and checks whether each of the 16 decoded signals matches each of the 16 busy signals. Then, the check circuits are arranged corresponding to the number of segments of 8. In this way, even if the number of ports increases due to a multi-system, the critical path of each check circuit can be shortened.
With advances in ECL gate integration technology, the time for one clock cycle can be reduced to, for example, 5 ns, making it possible to improve the performance of the entire system.

The present invention thus provides a main memory access priority control system that aims to alleviate the delay time in the priority cycle and reduce the hardware logistics for the control circuit.

[Means for solving problems]

FIG. 1 is a block diagram of a control circuit according to the main memory access priority control system of the present invention.

Each main memory control unit (MCU) 10, 11 is
It is assumed that it is composed of four segments (SEG), and each segment is composed of 16 memory banks. Then, access contention for each memory bank within the segment is checked in the next second priority cycle. That is, the 4-bit lower address signal (A3 to A3) latched in the latch circuit corresponding to the second access port
A0) is decoded using an intra-segment logical storage (LS) busy check circuit, and it is checked within the second priority cycle whether the decoded signal matches each busy signal of each memory bank. .

In the first priority cycle, the first
The operation of setting the request address to the access port 10 of the request address is possible within the request transfer cycle.

In the present invention, an accessed and free bus is selected first in the first priority cycle, but once a memory bank connected to that bus is accessed, even vector data For example, there is a high probability that that memory bank or other memory banks connected to the selected bus will be accessed later, and even if the conventional fine-grained control method is used, the same bus will be selected. , two consecutive checks for bus contention and memory bank busy status.
Even if it is performed separately into cycles (first and second priority cycles), the performance will not deteriorate. Instead, in the present invention, the bus conflict other check (BCOC) circuit 16 that resolves conflicts between buses is simply configured with a simple comparison circuit for the upper 3 bit address signals, and performs a memory bank busy check. If the LS/busy check circuit 13 is constructed from a simple decoder that decodes the lower 4-bit address signal,
The critical logic paths of each circuit can be shortened, and the amount of hardware can also be made extremely small.

[Effect]

In the present invention, in the output of the latch circuit 15 which is the first access port, that is, in the first priority cycle, bus contention corresponding to the segment is checked using the segment address, and the second access port which is the second access port corresponding to the segment is checked for bus contention corresponding to the segment. The BCOC circuit 16 checks whether the lower address within the segment can be set in the latch circuit 12. and the output of the second access port,
In other words, in the second priority cycle,
The LS busy check circuit 13 performs a busy check of the memory bank and checks for conflict conditions within the segment. Depending on whether this is possible or not, it is determined whether or not to send a request to the main storage device.

Particularly when vector data is the target, the performance does not deteriorate even if the bus contention check and the memory bank busy check are performed separately in the first and second priority cycles. Performance is improved by shortening the critical logic path of the check circuit that operates in each cycle and by reducing the length of the clock cycle.
Additionally, the amount of hardware can be reduced.

〔Example〕

Next, the main memory access priority control system of the present invention will be explained with reference to the drawings.

A computer system in which the present invention is applied has one or more central processing units (CPUs) connected to one or more main storage units (MSUs) via a main memory control unit (MCU). In particular, when one or more memory access requests are made from the central processing unit (CPU) or other external device per unit machine cycle, the present invention provides the above-mentioned method for controlling whether or not the access is possible. Concerning the control circuit within the MCU.

FIG. 1 is a block diagram of a control circuit according to the main memory access priority control system of the present invention. for example,
It has two main memory control units ( _{MCU), MCU 0 10} and MCU ₀ 11 _.
1 is divided into four division units called segments (SEG), and each segment (SEG0, SEG1,
SEG2, SEG3) are, for example, 16 Logical
It is connected to a memory bank called Storage (LS) (not shown). Each segment then has a corresponding bus (not shown). The latch circuit 14 in FIG. 1 corresponds to each segment, and the signal lines 110,
120, 130, and 140 correspond to each bus or each segment. When the valid signal is latched to the latch circuit 14 via the signal line 130, use of the corresponding bus and the memory bank connected thereto is permitted. Latch circuit 14 corresponds to latch circuit 35 of the conventional control circuit of FIG.

In this way, each MSU 10, 11 consists of 4 segments, and each segment consists of 16 memory banks, so it is connected to 64 memory banks, and MSU ₀ 10 and MSU ₁ 11 have a total of So it has 128 memory banks. the above
Although the numerical values of the number of MSUs, the above-mentioned number of segments, or the above-mentioned number of memory banks are not limited to these values, this embodiment will be described using the above-mentioned numerical values.

When accessing each memory bank, the latch circuit 12 (third
The intra-segment address latched in the latch circuit 36 of the conventional control circuit shown in the figure, that is, the 4-bit lower address signal (A3 to A0)
is decoded using an intra-segment logical storage busy check circuit 13 (hereinafter simply referred to as an LS busy check circuit), and it is checked whether the degoed signal matches each busy signal. In this busy check method using the LS busy check circuit 13,
If the memory bank is in the busy state, the read/write operation cannot be performed on that memory bank, but if it is not in the busy state, that is, in the ready state, the operation can be performed.

Since 16 memory banks are connected to each segment, when access is requested to two or more memory banks on the same memory bank at the same time, in the present invention, the selection of a memory bank that is not busy is performed by the LS - Executed using only the busy check circuit 13. Furthermore, since data cannot be simultaneously loaded onto commonly connected buses, bus contention occurs. In the conventional control method,
Bus contention for each bus and busy checks for each memory bank and checks for other contention conditions were performed simultaneously in the same cycle of the clock signal, ie, in a single priority cycle.
In the present invention, in the first priority cycle, the Bus Conflict & Other Check (BCOC)
The circuit 16 is used to check for bus contention and a bus is selected first, and in the second priority cycle, the LS busy check circuit 13 is used to execute a memory bank busy check. That is, in the present invention, the first access port 15
In the first priority cycle, the segment addresses set in , that is, the upper address signals A6, A5, and A4 are input to the BCOC circuit 16, and bus contention corresponding to the segment is checked, and the bus is selected first. . Then, the intra-segment addresses A3, A2,
Check whether A1 and A0 can be set. The intra-segment address, that is, the lower 4 bits of address signals A3, A2, A1, A0 are set in the latch circuit 12 of the second access port corresponding to the selected bus segment.
Then, in the next second priority cycle, the LS busy check circuit 13 is used to check for conflict conditions within the segment whose main purpose is to busy check the memory bank.
Depending on whether or not these are possible, it is determined whether or not to send a request to the MSU. The second priority cycle corresponds to a conventional priority cycle. In the first priority cycle, the first
The operation of setting the request address in the latch circuit 15, which is the access port of the transfer port, can be performed within the request transfer cycle. Therefore, the first priority cycle corresponds to a request transfer cycle in the conventional system, and the latch circuit 15 corresponds to a latch circuit (not shown) located one clock before the latch circuit 36 in the conventional control circuit. . Further, the BCOC circuit 16 corresponds to a bus conflict check circuit 37 and an other conflict check circuit 39 in a conventional control circuit.

When a memory access request is received from another external device, the address signal for the access request is a 7-bit (A6
~A0), of which upper A6, A5, and A3 specifying eight buses are set in the latch circuit 15 for at least the first access port. Then, in the first priority cycle, the upper address signals A6,
A5 and A3 are given to the BCOC circuit 16, and a 3-bit comparison circuit checks whether the code matches the code corresponding to the bus in use. Check if it is available. If the requested bus is available, select that bus. If a bus that is already being used by another access request is accessed, that access request will be forced to wait until use of that bus is permitted. but,
Once the use of a bus is permitted, if the target is vector data, there is a high probability that the next access request will also use the same bus, and performance will not deteriorate even if a bus is selected first. The BCOC circuit 16
Since it is constructed based on a comparison circuit, the critical logic path is short and the amount of hardware is small.

In the present invention, a bus contention check is performed in the first priority cycle, and a memory bank busy check is performed in the second priority cycle. The latch circuit 12 corresponding to the second access port is located within each segment.
Lower address signal specifying 16 memory banks
When A3, A2, A1, A0 are latched, the second
In the priority cycle, the LS busy check circuit 13 decodes the lower address signal and compares the decoded signal with each busy signal. In this case, the LS busy
The check circuit 13 can have an extremely small amount of hardware compared to the conventional logical storage busy check circuit 38, and can also shorten critical logic paths.

For example, the circuit shown in FIG. 2a is the LS busy check circuit 13 of the present invention, which inputs 4-bit address signals A3, A2, A1, A0, and
This circuit checks whether each of the 16 decoded signals matches the busy signals of the 16 memory banks in each segment.

Each gate is composed of emitter coupled logic (ECL), the maximum number of inputs to each gate is 4, and emitter coupled logic (ECL) is used to form OR logic by directly connecting the emitters of each gate. It is assumed that the maximum number of dots is also 4.

Four input signals of OR gate 20 (ADRS
BIT0 to 3) are signals that are all logic 0 when addresses A3, A2, A1, and A0 are all logic 0 (0000), and are signals that are all logic 0 when addresses A3, A2, A1, and A0 are all logic 0 (0000).
BIT0~3), addresses A3, A2, A1, A0 are 1
This signal is all logic 0 at address (0001). Four input signals of OR gate 22 (ADRS
BIT0~3), addresses A3, A2, A1, A0 are 2
A signal that is all logic 0 at address (0010),
Input signal of OR gate 23 (ADRSBIT0-3)
The address A3, A2, A1, A0 is the 3rd address (0011)
This is a signal that is all logic 0 when OR circuit 2
There are 16 OR circuits for each segment, including those for 0, 21, 22, and 23. The output of the OR gate 20 is the input signal (ADRS BIT0 ~
3) are all logic 0, they become logic 0 and are input to the NOR gate 24. Since the NOR gate 24 also receives a busy signal called BUSY0, when this busy signal is logic 0 and the output signal 201 of the OR gate 20 is logic 0, the output 240 of the NOR gate 24 becomes logic 1. At the same time, or gate 2
The output of 1 becomes logic 0 when all input signals (ADRS BIT0 to 3) are logic 0, and the output of NOR gate 25
Enter. Since a busy signal called BUSY1 is also input to the NOR gate 25, this busy signal is logic 0 and the output signal of the OR gate 21 is
When both 211 are logic 0, the output of NOR gate 25 is logic 1. Similarly, the output of the OR gate 22 becomes logic 0 when all the input signals (ADRS BIT0-3) are logic 0, and is input to the NOR gate 26. Since a busy signal called BUSY2 is also input to the NOR gate 26, this busy signal is logic 0 and the output signal 221 of the OR gate 22 is
When both are logic 0, the output 260 of the NOR gate 26
becomes logic 1. Similarly, the output of the OR gate 23 becomes logic 0 when all the input signals (ADRS BIT0 to 3) are logic 0, and is input to the NOR gate 27. Since a busy signal called BUSY3 is also input to the NOR gate 27, this busy signal is logic 0 and the output signal of the OR gate 23 is
When both 231 are logic 0, the output of NOR gate 27 is 270 is logic 1.

The maximum number of inputs to each OR gate is limited to four, but when ORing four address bits, only one gate is required, such as OR gate 20.

The outputs of the NOR gates 24, 25, 26, and 27 are input to the 4-input OR gate 28, so the output signal 280 of the OR gate 28 is a signal in which at least one of the outputs of the NOR gates is logic 1 and is logic 1. . There are a total of four gates that are the same as the OR gate 28, so if the outputs of these four OR gates are formed into OR logic using emitter dots as shown in the figure, 16 decoded signals can be obtained. and the busy signals of the 16 memory banks in each segment. Since the maximum is 4 when OR logic is formed by emitter dots, no gate is present on the output side of gate 28.

The delay time of the LS busy check circuit 13 in FIG. 2a is 3τ, which is the delay time for three gates, where τ is the delay time of a unit gate. Also,
The total number of gates is 129, regardless of the number of ports.

FIG. 2b is a table comparing the delay time and number of gates in the conventional LS busy check circuit (FIG. 4) and the LS busy check circuit of the present invention (FIG. 2a). Number of ports and
It is assumed that the number of SEGMENTs is the same. Therefore, the difference in the total number of gates is (417-129) x number of ports (number of SEGs).

As this table shows, in the present invention, the delay time in the priority determination cycle is alleviated, and the amount of hardware is reduced.

As described above, the present invention is a main memory access priority control method that is particularly effective for multi-systems in which there are a plurality of processing units that access memory within a vector computer, and vector data is stored in the same memory bank. It takes advantage of the fact that there is a very high probability that That is, in the present invention, an accessed and vacant bus is selected first in the first priority cycle.
Once the memory bank selected for that bus is accessed, if it is vector data, there is a high probability that that memory bank or other memory banks connected to the selected bus will be accessed later. Even if the conventional method uses a fine-grained control method, the same bus will be selected, and two consecutive cycles (first and second priority cycles) of checking bus contention and checking the busy state of the memory bank. Even if it is separated into two parts, the performance will not deteriorate. In the present invention, the BCOC circuit 16 that resolves contention between buses is simply
The LS busy check circuit 13, which performs a memory bank busy check, can be configured with a simple comparison circuit for bit address signals, and if it is configured with a simple decoder that decodes the lower 4-bit address signal, the critical The logical path can be shortened, and the amount of hardware can be extremely small.

In the present invention, the BCOC circuit 16 is operated in the first priority cycle, and the BCOC circuit 16 is operated in the first priority cycle.
Although the LS busy check circuit 13 is operated in the second priority cycle, the first priority cycle can be started from the latch of the address signal, and therefore corresponds to the request transfer cycle.

〔Effect of the invention〕

As described above, the present invention has the effect of easing the delay time in the priority cycle and reducing the amount of hardware for the control circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a control circuit according to the main memory access priority control method of the present invention, FIGS. 2 a and b are circuit diagrams of the LS/busy check circuit of the present invention, and FIG. 3 is a block diagram of a conventional control circuit. , Figure 4 shows the conventional LS・
FIG. 3 is a busy check circuit diagram. 10...MCU ₀ , 11...MCU ₁ , 12,1
4, 15...Latch circuit, 13...LS busy check circuit, 16...Bus conflict other check circuit.

Claims (1)

[Scope of Claims] 1. When a plurality of memory access requests are received from a plurality of processing devices logically connected to the main storage unit (MSU), control is made as to whether or not transmission can be made to the main storage unit (MSU). a first access request port 15 that at least temporarily holds the segment address of the memory access request from each of the processing units; a first control means 16 for controlling, in a first priority cycle, a contention condition for a destination segment determined by the address of an access request; Second access request port 12 to be held at least temporarily
and a second control means 13 connected to the output of the second access request port for controlling contention conditions within each of the segments in a second priority cycle, and controlling contention conditions for the segments within the segments. When running in different clock cycles, all processing unit requests are checked for conflicts at their destination segment address, and
A main memory access priority control system characterized in that an intra-segment bank busy check is performed from a port corresponding to each segment by setting the second access request port. 2. Claim 1, characterized in that the first control means 16 includes at least a comparison circuit that compares the segment addresses A6, A5, A4 of the access request with a segment address indicating the usage state of the bus. Main memory access priority control method described. 3. The second control means 13 decodes the intra-segment addresses A3, A2, A1, and A0 of the access request, and determines whether the generated decoded signal matches the busy signal corresponding to each memory bank. 2. The main memory access priority control system according to claim 1, wherein the main memory access priority control system is a busy check circuit that checks the main memory access priority level. 4. The main memory access priority control system according to claim 1, wherein the first priority cycle corresponds to a request transfer cycle.