JPS6478050A - Error generation circuit - Google Patents

Error generation circuit

Info

Publication number
JPS6478050A
JPS6478050A JP23550987A JP23550987A JPS6478050A JP S6478050 A JPS6478050 A JP S6478050A JP 23550987 A JP23550987 A JP 23550987A JP 23550987 A JP23550987 A JP 23550987A JP S6478050 A JPS6478050 A JP S6478050A
Authority
JP
Japan
Prior art keywords
error
bits
generated
signal
event
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23550987A
Other languages
Japanese (ja)
Inventor
Shiyouji Kudou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23550987A priority Critical patent/JPS6478050A/en
Publication of JPS6478050A publication Critical patent/JPS6478050A/en
Pending legal-status Critical Current

Links

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  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To perform the correct test of an LSI for a function to distinguish an alarm informing signal from data by providing a signal generating means which generates and outputs an event in which the (n) bits of an error are generated within an error detecting period for (m) times. CONSTITUTION:At the signal generating means 1, the event in which the (n) bits, for example, two bits of the error with, for example, a level 0, are generated within the error detecting period is generated and outputted for (m) times, for example, two times continuously. The signal is inputted to the LSI to decide the event in which, for example, the two bits of the error with a level 0 are generated within the error detecting period as the data when such signal is inputted for two times continuously, and it is recognized that it is decided as the data. In such a way, it is possible to perform a correct test.
JP23550987A 1987-09-18 1987-09-18 Error generation circuit Pending JPS6478050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23550987A JPS6478050A (en) 1987-09-18 1987-09-18 Error generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23550987A JPS6478050A (en) 1987-09-18 1987-09-18 Error generation circuit

Publications (1)

Publication Number Publication Date
JPS6478050A true JPS6478050A (en) 1989-03-23

Family

ID=16987050

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23550987A Pending JPS6478050A (en) 1987-09-18 1987-09-18 Error generation circuit

Country Status (1)

Country Link
JP (1) JPS6478050A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8218163B2 (en) 2006-05-18 2012-07-10 Ricoh Co., Ltd. Operating apparatus, controlling operating apparatus, communication system, and managing communication system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8218163B2 (en) 2006-05-18 2012-07-10 Ricoh Co., Ltd. Operating apparatus, controlling operating apparatus, communication system, and managing communication system

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