JPS6477025A - Liquid crystal panel structure - Google Patents

Liquid crystal panel structure

Info

Publication number
JPS6477025A
JPS6477025A JP23402187A JP23402187A JPS6477025A JP S6477025 A JPS6477025 A JP S6477025A JP 23402187 A JP23402187 A JP 23402187A JP 23402187 A JP23402187 A JP 23402187A JP S6477025 A JPS6477025 A JP S6477025A
Authority
JP
Japan
Prior art keywords
liquid crystal
wiring pattern
electrode
bump
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23402187A
Other languages
Japanese (ja)
Other versions
JP2674033B2 (en
Inventor
Katsuma Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62234021A priority Critical patent/JP2674033B2/en
Publication of JPS6477025A publication Critical patent/JPS6477025A/en
Application granted granted Critical
Publication of JP2674033B2 publication Critical patent/JP2674033B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Wire Bonding (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To prevent the short circuit between each wiring pattern or between the wiring pattern and an electrode pad by placing the electrode pad of an IC on two sides being parallel to each other of the IC, and loading this IC on a substrate of a liquid crystal display panel through an adhesive agent in which conductive fine particles have been mixed by face-down. CONSTITUTION:Electrode pads 7 of a liquid crystal driving use IC in which a bump has been formed are arranged in good order along two sides of an external form of the liquid crystal driving use IC. Electrode terminals 5 of a liquid crystal display panel opposed to this bump are also arranged in good order in two lines, and it does not occur that a wiring pattern 11 for connecting the electrode terminal 5 and an electrode 10 in the liquid crystal display panel is placed vertically and horizontally. In such a way, there is no possibility that the separate wiring pattern 11 and the bump are short-circuited, and in the same way, there is no possibility either that each separate wiring pattern is short-circuited.
JP62234021A 1987-09-18 1987-09-18 Liquid crystal device Expired - Lifetime JP2674033B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234021A JP2674033B2 (en) 1987-09-18 1987-09-18 Liquid crystal device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234021A JP2674033B2 (en) 1987-09-18 1987-09-18 Liquid crystal device

Publications (2)

Publication Number Publication Date
JPS6477025A true JPS6477025A (en) 1989-03-23
JP2674033B2 JP2674033B2 (en) 1997-11-05

Family

ID=16964316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234021A Expired - Lifetime JP2674033B2 (en) 1987-09-18 1987-09-18 Liquid crystal device

Country Status (1)

Country Link
JP (1) JP2674033B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04242945A (en) * 1991-01-08 1992-08-31 Sharp Corp Semiconductor device
JPH04269843A (en) * 1991-02-26 1992-09-25 Semiconductor Energy Lab Co Ltd Mounting structure of ic chip
KR100232678B1 (en) * 1996-12-18 1999-12-01 구본준 A structure and a method of ridged bump
JP2005203745A (en) * 2004-01-15 2005-07-28 Samsung Electronics Co Ltd Drive chip and display device comprising it
US7482541B2 (en) 2004-03-17 2009-01-27 Seiko Epson Corporation Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61123538U (en) * 1985-01-21 1986-08-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61123538U (en) * 1985-01-21 1986-08-04

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04242945A (en) * 1991-01-08 1992-08-31 Sharp Corp Semiconductor device
JPH04269843A (en) * 1991-02-26 1992-09-25 Semiconductor Energy Lab Co Ltd Mounting structure of ic chip
KR100232678B1 (en) * 1996-12-18 1999-12-01 구본준 A structure and a method of ridged bump
JP2005203745A (en) * 2004-01-15 2005-07-28 Samsung Electronics Co Ltd Drive chip and display device comprising it
US7482541B2 (en) 2004-03-17 2009-01-27 Seiko Epson Corporation Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus

Also Published As

Publication number Publication date
JP2674033B2 (en) 1997-11-05

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