JPS6474649A - Sector buffer control system - Google Patents

Sector buffer control system

Info

Publication number
JPS6474649A
JPS6474649A JP23166887A JP23166887A JPS6474649A JP S6474649 A JPS6474649 A JP S6474649A JP 23166887 A JP23166887 A JP 23166887A JP 23166887 A JP23166887 A JP 23166887A JP S6474649 A JPS6474649 A JP S6474649A
Authority
JP
Japan
Prior art keywords
buffer
transfer
data
sector
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23166887A
Other languages
Japanese (ja)
Other versions
JPH0578859B2 (en
Inventor
Naotatsu Hatsutori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23166887A priority Critical patent/JPS6474649A/en
Publication of JPS6474649A publication Critical patent/JPS6474649A/en
Publication of JPH0578859B2 publication Critical patent/JPH0578859B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To shorten data transfer time without increasing the amount of circuits by simultaneously performing data transfer processing between a disk device and a sector buffer and that between the sector buffer and a system bus. CONSTITUTION:When a FF 7 is set to logical '1' to command transfer to and from a system buffer 12, data on a disk 10 is stored in a sector buffer 1 designated by a buffer switching circuit 8 and is counted. A flag 5 is set to logical '1' to interrupt transfer when the transfer of one-sector components of data is terminated, and the transfer is restarted when the buffer 1 is switched to the buffer 2 by the circuit 8. Simultaneously, data is transferred from the buffer 1 to the bus 12 by the FF 7 and the flag 5; and when the flag 5 is set to logical '0', data is transferred from the buffer 2 to the bus 12. Thus, the transfer between the disk and the buffer and that between the buffer and the system bus are simultaneously performed to shorten the processing time without increasing the quantity of circuits.
JP23166887A 1987-09-16 1987-09-16 Sector buffer control system Granted JPS6474649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23166887A JPS6474649A (en) 1987-09-16 1987-09-16 Sector buffer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23166887A JPS6474649A (en) 1987-09-16 1987-09-16 Sector buffer control system

Publications (2)

Publication Number Publication Date
JPS6474649A true JPS6474649A (en) 1989-03-20
JPH0578859B2 JPH0578859B2 (en) 1993-10-29

Family

ID=16927106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23166887A Granted JPS6474649A (en) 1987-09-16 1987-09-16 Sector buffer control system

Country Status (1)

Country Link
JP (1) JPS6474649A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421274B1 (en) 2001-03-23 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and reading and writing method thereof
US6691205B2 (en) * 2001-03-05 2004-02-10 M-Systems Flash Disk Pioneers Ltd. Method for using RAM buffers with simultaneous accesses in flash based storage systems

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6691205B2 (en) * 2001-03-05 2004-02-10 M-Systems Flash Disk Pioneers Ltd. Method for using RAM buffers with simultaneous accesses in flash based storage systems
US6421274B1 (en) 2001-03-23 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device and reading and writing method thereof

Also Published As

Publication number Publication date
JPH0578859B2 (en) 1993-10-29

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term