JPS6474622A - Branch history table controller - Google Patents

Abstract

PURPOSE:To eliminate contention between a read request and a write request by using private ports corresponding to a read means and a write means to simultaneously operate the read operation of the read means and the write operation of the write means. CONSTITUTION:When instruction prefetch is started, an address from an instruction counter 2 is received through a read address port R to read out a branch instruction address 51, a branch destination address 52, and an effective bit flag 53 from a branch history table 5. When a branch instruction is decided by a control part 7, the address 52 is sent to a storage control part 10. The branch instruction address, the branch destination address, and effective bit flag information are written in a write register 4 from an operation part 1 at the time of the end of the execution cycle of the branch instruction. The branch instruction address stored in the register 4 is inputted from an address port W of the table 5 and the contents of the register 4 are registered in the table 5. This register processing is executed without interrupting the read processing even during the read processing of the address 52.