JPS6437651A - Memory access control circuit - Google Patents

Memory access control circuit

Info

Publication number
JPS6437651A
JPS6437651A JP19406787A JP19406787A JPS6437651A JP S6437651 A JPS6437651 A JP S6437651A JP 19406787 A JP19406787 A JP 19406787A JP 19406787 A JP19406787 A JP 19406787A JP S6437651 A JPS6437651 A JP S6437651A
Authority
JP
Japan
Prior art keywords
memory access
respective ports
contents
buffer
ports
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19406787A
Other languages
Japanese (ja)
Other versions
JP2632859B2 (en
Inventor
Masao Koyabu
Hiroyuki Egawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62194067A priority Critical patent/JP2632859B2/en
Publication of JPS6437651A publication Critical patent/JPS6437651A/en
Application granted granted Critical
Publication of JP2632859B2 publication Critical patent/JP2632859B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Abstract

PURPOSE:To recognize the operation of respective ports and to simplify the control procedure of respective ports by comparing the contents of data in a memory access buffer which are the contents of respective ports. CONSTITUTION:In order to check whether a precedently started memory access is completed or not, a start address of the memory access buffer 2 starting the memory access previously specified by a microprogram is sent from a microprocessor 1 to a bus 12. The start addresses of the buffer 2 previously specified by the microprogram are sent from respective ports 31-34 to a comparator 6. The compared result output of the comparator 6 and information V indicting whether the port concerned out of the ports 31-34 is started or stopped are supplied to an AND gate 7. When the AND operation of both the contents is executed, whether the port holding the address concerned ends the memory access or not is checked.
JP62194067A 1987-08-03 1987-08-03 Memory access control circuit Expired - Lifetime JP2632859B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194067A JP2632859B2 (en) 1987-08-03 1987-08-03 Memory access control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194067A JP2632859B2 (en) 1987-08-03 1987-08-03 Memory access control circuit

Publications (2)

Publication Number Publication Date
JPS6437651A true JPS6437651A (en) 1989-02-08
JP2632859B2 JP2632859B2 (en) 1997-07-23

Family

ID=16318406

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194067A Expired - Lifetime JP2632859B2 (en) 1987-08-03 1987-08-03 Memory access control circuit

Country Status (1)

Country Link
JP (1) JP2632859B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697166A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Memory lock system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697166A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Memory lock system

Also Published As

Publication number Publication date
JP2632859B2 (en) 1997-07-23

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