JPS6473733A - Ic package - Google Patents

Ic package

Info

Publication number
JPS6473733A
JPS6473733A JP23310787A JP23310787A JPS6473733A JP S6473733 A JPS6473733 A JP S6473733A JP 23310787 A JP23310787 A JP 23310787A JP 23310787 A JP23310787 A JP 23310787A JP S6473733 A JPS6473733 A JP S6473733A
Authority
JP
Japan
Prior art keywords
layer
pattern
patterns
position detecting
prevented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23310787A
Other languages
Japanese (ja)
Other versions
JPH0691124B2 (en
Inventor
Keizo Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23310787A priority Critical patent/JPH0691124B2/en
Publication of JPS6473733A publication Critical patent/JPS6473733A/en
Publication of JPH0691124B2 publication Critical patent/JPH0691124B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the position detecting patterns of layers other than a layer whose position is to be detected from being detected by mistake by a method wherein the forms of the position detecting patterns of every layer are made to differ from each other. CONSTITUTION:A position detecting pattern 12 and a position detecting pattern having a form different from that of the pattern 12 are arranged alternately in the direction of the same diagonal line of a package 1 on every layer of the package 1. Whereupon, the same pattern can be prevented from being displayed in a pattern detecting range 6 in the case of detection of the position of each layer at the time of bonding. Thereby, it can be prevented to detect the patterns of other layers by mistake at the time of detection of the patterns of every layer. Therefore, the generation of bonding deviation can be prevented.
JP23310787A 1987-09-16 1987-09-16 IC package Expired - Fee Related JPH0691124B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23310787A JPH0691124B2 (en) 1987-09-16 1987-09-16 IC package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23310787A JPH0691124B2 (en) 1987-09-16 1987-09-16 IC package

Publications (2)

Publication Number Publication Date
JPS6473733A true JPS6473733A (en) 1989-03-20
JPH0691124B2 JPH0691124B2 (en) 1994-11-14

Family

ID=16949884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23310787A Expired - Fee Related JPH0691124B2 (en) 1987-09-16 1987-09-16 IC package

Country Status (1)

Country Link
JP (1) JPH0691124B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5496777A (en) * 1993-08-26 1996-03-05 Oki Electric Industry Co., Ltd. Method of arranging alignment marks
US6316735B1 (en) 1996-11-08 2001-11-13 Ricoh Company, Ltd. Semiconductor chip mounting board and a semiconductor device using same board
JP2007019415A (en) * 2005-07-11 2007-01-25 Renesas Technology Corp Semiconductor device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5496777A (en) * 1993-08-26 1996-03-05 Oki Electric Industry Co., Ltd. Method of arranging alignment marks
US6316735B1 (en) 1996-11-08 2001-11-13 Ricoh Company, Ltd. Semiconductor chip mounting board and a semiconductor device using same board
JP2007019415A (en) * 2005-07-11 2007-01-25 Renesas Technology Corp Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JPH0691124B2 (en) 1994-11-14

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees