JPS5791269A - Print controller - Google Patents

Print controller

Info

Publication number
JPS5791269A
JPS5791269A JP16751380A JP16751380A JPS5791269A JP S5791269 A JPS5791269 A JP S5791269A JP 16751380 A JP16751380 A JP 16751380A JP 16751380 A JP16751380 A JP 16751380A JP S5791269 A JPS5791269 A JP S5791269A
Authority
JP
Japan
Prior art keywords
type
belt
pulse
outputs
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16751380A
Other languages
Japanese (ja)
Inventor
Akinori Kamata
Nobuo Ushiba
Minoru Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16751380A priority Critical patent/JPS5791269A/en
Publication of JPS5791269A publication Critical patent/JPS5791269A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To detect the using side or misapplication of a type belt prior to the printing by adding a home clock and a type belt operation indicating circuit or an abnormality detection circuit.
CONSTITUTION: During the A side setting of a type belt 2 or the normal mounting thereof, a home clock signal 6' forms three pulses with respect to a type clock signal 5; the first between those of the signal 5 and then, the second and third each between those thereof dropping one. Consequently, the outputs QC and QD of a shift register 14 of a reference position checking circuit are 0 (without pulse) and 1 (with pulse) and an AND gate 15 of the reference position checking circuit receiving both the outputs produce an output for normal or belt A side operation. In the case of the B side type setting of the belt 2 or the opposite mounting thereof, the home clock signal 6" forms first and second pulses side by side and then, the third pulse dropping one. Thus, the outputs QC and QD are 1 and 1 emitting the B side type setting or abnormality signal AL.
COPYRIGHT: (C)1982,JPO&Japio
JP16751380A 1980-11-28 1980-11-28 Print controller Pending JPS5791269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16751380A JPS5791269A (en) 1980-11-28 1980-11-28 Print controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16751380A JPS5791269A (en) 1980-11-28 1980-11-28 Print controller

Publications (1)

Publication Number Publication Date
JPS5791269A true JPS5791269A (en) 1982-06-07

Family

ID=15851070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16751380A Pending JPS5791269A (en) 1980-11-28 1980-11-28 Print controller

Country Status (1)

Country Link
JP (1) JPS5791269A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4759647A (en) * 1986-10-22 1988-07-26 International Business Machines Corporation Dual pitch impact printer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4759647A (en) * 1986-10-22 1988-07-26 International Business Machines Corporation Dual pitch impact printer

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