JPS5385163A - Packaging method of ic chip - Google Patents

Packaging method of ic chip

Info

Publication number
JPS5385163A
JPS5385163A JP15975076A JP15975076A JPS5385163A JP S5385163 A JPS5385163 A JP S5385163A JP 15975076 A JP15975076 A JP 15975076A JP 15975076 A JP15975076 A JP 15975076A JP S5385163 A JPS5385163 A JP S5385163A
Authority
JP
Japan
Prior art keywords
chip
packaging method
leads
bonding holes
covering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15975076A
Other languages
Japanese (ja)
Inventor
Naoyuki Echigo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP15975076A priority Critical patent/JPS5385163A/en
Publication of JPS5385163A publication Critical patent/JPS5385163A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To enable an IC chip to be packaged easily even in the case of leads of intricate shapes by constituting bonding holes on one side of a film thereby increasing total thickness at the time of covering the bonding holes with leads and performing molding.
COPYRIGHT: (C)1978,JPO&Japio
JP15975076A 1976-12-30 1976-12-30 Packaging method of ic chip Pending JPS5385163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15975076A JPS5385163A (en) 1976-12-30 1976-12-30 Packaging method of ic chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15975076A JPS5385163A (en) 1976-12-30 1976-12-30 Packaging method of ic chip

Publications (1)

Publication Number Publication Date
JPS5385163A true JPS5385163A (en) 1978-07-27

Family

ID=15700433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15975076A Pending JPS5385163A (en) 1976-12-30 1976-12-30 Packaging method of ic chip

Country Status (1)

Country Link
JP (1) JPS5385163A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60154536A (en) * 1984-01-24 1985-08-14 Toshiba Corp Wiring process of integrated circuit element
JPH09199548A (en) * 1996-01-23 1997-07-31 Nec Corp Gang bonding apparatus
US6396159B1 (en) 1997-06-27 2002-05-28 Nec Corporation Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60154536A (en) * 1984-01-24 1985-08-14 Toshiba Corp Wiring process of integrated circuit element
JPH09199548A (en) * 1996-01-23 1997-07-31 Nec Corp Gang bonding apparatus
US6396159B1 (en) 1997-06-27 2002-05-28 Nec Corporation Semiconductor device

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