JPS64731B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction address tracing method.

In an instruction processing device that reads and executes instructions stored in a memory, there are times when it is necessary to know in what order the instructions were executed. Conventionally, for this purpose, there is a system in which addresses of executed instructions are stored in memory in order, so that instructions executed in the past can be traced.
Since the number N of addresses stored in the memory is limited, the addresses of the latest N executed instructions are stored, and the addresses older than that are rewritten. However, with this method, if an instruction that creates a loop is included between the final part of the trace and the part you want to observe, many addresses will be saved in the loop part, and the address will not be saved. This has the disadvantage that the memory that is used for this purpose ends up containing only the trace of the loop portion, and the portion to be observed is rewritten by the trace of the loop portion and is not saved.

An object of the present invention is to provide an instruction address tracing method that can grasp the flow of the entire program and read the order of instruction execution immediately before the end of the trace, no matter what kind of loop is configured. It is in.

A feature of this invention is that in order to store the addresses of executed instructions, a memory with addresses of the same capacity as the memory that stores the instructions is prepared, and the number of instructions at each address is stored in this memory. It attempts to trace instructions by writing whether they were executed.

Next, embodiments of the present invention will be described in detail using the drawings. FIG. 1 shows a block diagram of an address storage device which is an embodiment of the present invention. In the figure, 2 is a control memory that stores the program, 4 is a counter that counts up by 1 each time one instruction is executed, and 3 is an area where the value of counter 4 can be stored, which is stored in control memory 1. It is a trace memory that has a number of instructions.

The instruction processing device 1 gives a read address to the control memory 2 through the address line 5,
Read instructions. At this time, the address also serves as the address of the trace memory 3. The counter 4 is incremented by a count up signal 11 caused by an instruction execution end signal 8 that is output for each instruction, and the value 7 is written into the trace memory 3 by a write permission signal 10 caused by an instruction read signal 9 from the instruction processing device 1. The value of counter 4 indicates the number of times the current instruction has been executed. Furthermore, the writing process to the trace memory 3 is terminated by an arbitrary trace end signal 12.

The number of words in the trace memory 3 is required to be the same as the number of words in the control memory 2. Furthermore, since the counter 4 is always incremented by 1, it is desirable that the number of bits be as large as possible.
The number of bits per word of trace memory 3 is required to be the same as count 4.

During normal operation, when the instruction processing device 1 reads an instruction from the control memory 2, the trace memory 3
A value 7 indicating the number of the instruction currently being executed is stored at the same address. Therefore, each address in the trace memory 3 stores the counter value 7 when the same address (same instruction) in the control memory was last read and executed. However, since the counter 4 returns to zero due to overflow, it is necessary to have a number of bits that rotate with a sufficient period so that when the trace memory is dumped later, no confusion will be recorded.

When the operation of the instruction processing device stops or when the trace end signal 12 is received, the value of the counter 4 and the contents of the trace memory 3 at that time are saved. If there is a portion forming a loop between the end of the trace and the portion to be observed, the loop portion contains the counter value 7 when the loop was last passed through. Therefore, if you search for an address that is smaller than the count value stored in the loop entry address and has a value closest to that value,
This is the address immediately before entering the loop.
It is also possible to calculate how many times the loop has been passed from the value immediately before entering the loop, the number of steps in the loop, and the count value left at the address in the loop. Furthermore, by looking at the entire trace memory, it is possible to read the flow of the entire program from the count value, and it is also possible to find parts that have not been passed at all.

FIGS. 2a and 2b illustrate the relationship between instructions forming a loop and trace memory. The address indicates the address of the instruction in the control memory 2. As shown in Figure 2a, the address
If the loop is executed multiple times between 1004 and 1008, looking at the contents of trace memory, the address
The values are far apart between 1003 and 1004, indicating that the loop entered from address 1003. Counter value is 16
It is expressed in decimal notation. and by other means
If we know that address 1008 is the loop end address, we can calculate that the loop has been passed four times from the difference between the values at addresses 1003 and 1004. Furthermore, when the instruction moves as shown in Figure 2b, it is clear from the contents of the trace memory that for the loop starting at address 1006, the last execution immediately before entering the loop was at address 1004, and the loop starts at address 1006. You can read the situation at the time of entry.

With the configuration as described above, the following effects can be obtained in the present invention.

1. Programs can be traced no matter what kind of loops are configured.

2. Can read the flow of the entire program and the parts that have not been passed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an instruction address trace system showing one embodiment of the present invention. FIG. 2a is a diagram showing an example of program tracing, and FIG. 2b is a diagram showing another example of program tracing. Explanation of symbols 1...Instruction processing device, 2...Control memory, 3...Trace memory, 4...
Counter, 5...Instruction address line.

Claims (1)

[Claims] 1. A method for tracing the execution of a program stored in a program memory, in which a count is incremented each time a programmed instruction is executed, regardless of the type of instruction, and the execution order of the instructions is determined. and a trace memory having a storage area corresponding to the number of instructions in the program memory, and each time an instruction is executed, storage in the trace memory corresponds to an address in the program memory where the instruction is stored. By storing the value of the counter at that time in an area, and even if an instruction at the same address in the program memory is executed multiple times, the value of the counter is overwritten in the corresponding storage area of the trace memory. , a program execution tracing method characterized by analyzing the execution order of program instructions using limited trace memory. 2. The trace memory is characterized in that whether or not writing of the value of the counter is permitted is controlled based on a signal that prohibits execution of tracing, and instructions in an arbitrary range of the program memory are traced. A program execution tracing method according to claim 1.