JPH01321531A - State information history circuit - Google Patents

Abstract

PURPOSE:To obtain state information necessary for the analysis of the abnormality or faults even when it is occurred during the error processing by dividing a memory circuit into two pieces at the time point when a first error occurs and storing the state information on the subsequent error processing actions. CONSTITUTION:A memory circuit 1 is divided into two pieces when the first error occurs. The information necessary for the analysis of the first error is stored in a 1/2 area X preceding an address A where the first error occurred. While the other 1/2 area Y stores the state information on the error processing actions. When an error occurs during an error processing action, a control circuit 8 stops the transmission a write pulse signal 802 and a write instruction signal 804 to the applied to an address circuit 2. Thus the storing action of the state information is stopped to the circuit 1. In this case, the circuit 1 stores both the state information necessary for the analysis of the first error and the state information necessary for the analysis of the error occurred during an error processing action.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a state information history circuit, and particularly to a state information history circuit that indicates the state of an information processing device. The present invention relates to a state information history circuit having a storage circuit that sequentially stores FX information.

Conventionally, in this type of state information N-history circuit, the number of state information histories stored in the memory circuit corresponds to the number of words in the memory circuit. Control was then performed to stop the storage operation in response to the occurrence of the first error.

However, in this case, the history of status information during subsequent error handling operations is not stored, so if an abnormality or failure occurs during error handling operations, the information necessary to investigate the cause etc. cannot be obtained. There was a drawback that there was no This has the disadvantage that error analysis becomes difficult and takes an excessive amount of time.

An object of the present invention is to provide a status information history circuit that can obtain status information necessary for analysis even if an abnormality or failure occurs during error processing.

Fish Elm 11 Relative The status information III history circuit of the present invention is a status information H history circuit having a storage means for sequentially storing status information indicating the status of an information processing device, and is a status information H history circuit that responds to the occurrence of an error in the information processing device. and a writing means for writing the state information to an area other than the area of the storage means in which the state information necessary for analyzing the error is stored.

juju week Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system diagram showing the configuration of an embodiment of a state information history circuit according to the present invention. In the figure, the state information history circuit according to an embodiment of the present invention includes a memory circuit 1, an address circuit 2, an increment circuit 3, an addition port 1184,
The divided address holding circuit 5, the comparison circuit 6, and the selection port l/
87 and a control circuit 8.

The storage circuit 1 stores status information 101 sent from each unit in the information processing device at a designated address, and outputs status information 102 from the designated address.

The address circuit 2 specifies an address for the storage circuit 1 and sends out an address signal 201.

The increment circuit 3 increments the address signal 201 sent from the address circuit 2, and sends out an increment l- signal 301 as the result.

The adder circuit 4 further adds a number of words that is half the number of words of the memory circuit 1 to the increment signal 301 sent from the increment circuit 3, and sends out an addition address signal 401.

The divided address holding circuit 5 holds the addition address signal 401 sent from the addition circuit 4 in response to a write instruction signal 805 from the control circuit 8.

The comparison circuit 6 compares the increment signal 301 and the divided address signal 501 sent from the divided address holding circuit 5, and sends out a match signal 601 if the comparison result shows a match.

The selection circuit 7 selects one of the increment signal 301, the addition address signal 401, and the successive address signal 801, and sends it to the address circuit 2 as the selected address signal 701.

The control circuit 8 controls the operation of each circuit.

The operation of the state information history circuit having such a configuration will be explained in detail by dividing it into two operations: a write operation and a read operation.

(1) Write operation The write operation of the status information 101 to the storage circuit 1 in the normal operating state where no error has occurred in the information processing device is as follows:
First, a write instruction is given to the control circuit 8 from the control signal 901, and the control circuit 8 sends a write pulse signal 802 to the storage circuit 1. At the same time, the control circuit 8 outputs a selection signal 8
03, the selection circuit 7 outputs an increment signal 30.
1 is selected, and an increment 1 signal 301 is sent to the address circuit 2 as a selection address signal 701.

Furthermore, the increment signal 301 selected by the write instruction signal 804 is held in the address circuit II@2. However, in the normal operating state, the address signal 201 of the memory circuit 1 is incremented by 1 every clock cycle, and the state information 101 for each clock cycle is sequentially stored in each address of the memory circuit 1.

Furthermore, when the status information 101 is stored for all addresses of the storage circuit 1, the address signal 201 returns to the first address again and the write operation is continued. In this case, previously stored state information will be erased, but this is not a problem since it will be erased in the oldest order.

Next, the operation when an error occurs in the information processing device is as follows: When the error is reported to the control circuit 8 by the control signal 901, the control circuit 8 internally takes in the address No. 18 201.
At the same time, the control circuit 8 outputs the write instruction signal 805 to the divided address holding circuit 5 for one clock cycle, and further outputs the write instruction signal 805 to the adder circuit 4 in response to the increment signal 301.
Thus, the added address signal 401 obtained by adding half the number of words of the memory circuit 1 is held in the divided address holding circuit 5.

In this case, the adder circuit 4 increments the increment signal 3
If the address resulting from addition to 01 overflows (carries up), the overflow signal 402 is sent to the control circuit 8.
Send to.

Further, the control circuit 8 enables a match signal 601 that is an output signal of the comparison result of the comparison circuit 6 that compares the increment signal 301 and the divided address signal 501. Even after the error occurs, the control circuit 8 continues to perform the above-described operations and further advances the storage operation of the status information 101.

In other words, the storage circuit 1 also stores state information during the error handling operation after an error occurs.

As the storage operation progresses, there are times when the increment signal 301 and the divided address signal 501 match. Record of this time +! The address of circuit 1 is a divided address of an area where status information during error handling operation can be stored.From the next address onwards, this area is used because the status information necessary for analysis when an error first occurs is stored. Therefore, when the control circuit 8 receives the match signal 601, it internally holds it and also outputs the selection signal 803.
is changed, and the addition address signal 401 is sent to the address circuit 2 via the selection circuit 7. In other words, the area in which status information necessary for analysis when an error first occurs is skipped, and the area in which status information during error processing is stored is written again.

The above write operation will be explained using FIG. 2. FIG. 2 is a conceptual diagram showing state information stored in the storage circuit 1 of FIG. 1.

As shown in the figure, from the time when the first error occurs, the memory circuit 1 is divided into 1/2, and the 1/2 area X before address A where the first error occurs (that is, from address B to ) stores the status information necessary for analysis when the first error occurs, and the other half of the area Y (that is, from addresses A to B) stores status information during error handling operation. It is.

Here, if another error occurs during the error processing operation and the error is reported by the control signal 901, the control circuit 8 sends the write pulse signal 802 and the address circuit 2
Stops sending the write instruction signal 804 to.

Then, the operation of storing state information in the memory circuit 1 is stopped. In this case, the storage circuit 1 stores state information necessary for analyzing the first error occurrence and state information necessary for analyzing the error occurrence during the error processing operation.

In addition, when the error handling operation ends normally, the normal end is reported by the control signal 901, and the control circuit 8 clears the error address and match signal held internally at the time of the error occurrence, and the comparison circuit 6 The match signal 601 of . As a result, the storage operation continues and the normal operating state is returned.

(2) Read operation Regarding the read operation, depending on the situation where the error occurred,
Since the storage state of the state information in the memory circuit 1 is different, it is necessary to distinguish between various cases. These can be divided into four cases, which cover all cases.

That is, there are four types of readout methods depending on the values of the address overflow signal 402 from the adder circuit 4 held in the control circuit 8 and the match signal 601 from the comparator circuit 6.

These will be explained using FIGS. 2 and 3. In Figure 2, the address where the error first occurred is A,
Address advanced by 1/2 word + 1 from address A,
That is, let the divided address be B, and let C be the address when an error occurs during the error processing operation and the address circuit 2 is stopped. Then, the state necessary for analysis when the first error occurs - h11 report X and the state in which error processing is in progress = hv report Y
will be stored in the area shown by ■ in FIG.

The read operation can be controlled by the address overflow signal 402 and the match signal 601 held in the control circuit 8 as shown in (1) to (4) in FIG.

Here, the case of ■ will be explained as an example.

In case (2), since both the address overflow signal 402 and the match signal 601 are [1], the state information is stored in all areas (all words) of the storage circuit 1. The area X in which the status information necessary for analysis when the first error occurs is stored in the range from the address B to the address Ai, as shown by ▪ in FIG. 3, and is stored in chronological order.

In this case, control circuit 8 reads address B from divided address holding circuit 5, sets address B in address circuit 2 by read address signal 801, and reads status information. Since the number of words from address B to address A is 1/2 of the number of words in memory circuit 1, address circuit 2 is incremented by that number of words, ,I! By iJ road 3-
The state information is incremented by 1, and all status information is sequentially output from area X.

Next, the area Y in which the status information during the error processing operation is stored is in the range from address C to address C-t, as shown by ◯ in FIG. 3, and is stored in chronological order. This is because when the address circuit 2 stops, it counts up by +1 and stops, so the address range is like this.

In this case, the control circuit 8 internally holds the address C.
is read out and set in the address circuit 2 by the address signal 801, and the status information is read out.Since the number of words from address C to address C-1 is 1/2 of the memory circuit 1, the address circuit is divided by the number of words. 2 is incremented by +1 by the increment circuit 3, and all state information is read out from the area Y.

As described above, the control circuit 8 can also control the readout for the other cases (1) to (2).

In this embodiment, the area necessary for error analysis is set to 1/2 the number of words of the memory circuit 1, but it is obvious that it may be set to another number of words, for example, 1/3 the number of words.

In addition, in this embodiment, the status information after the first error occurs is continuously stored, but in response to external selection commands, etc., the same control as the conventional status information history circuit (
In other words, it is obvious that a configuration may be adopted in which the storage operation is stopped when an error first occurs.

As explained above, the present invention divides the memory circuit into two at the moment an error occurs, and also stores the status information during the subsequent error handling operation. Even if an abnormality or failure occurs, the status information necessary for analysis can be obtained, so the time required for error analysis can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of a state information history circuit according to an embodiment of the present invention, FIG. 2 is a conceptual diagram showing state information stored in the storage circuit of FIG. 1, and FIG. 3 is a diagram showing the inside of the storage circuit. 12 is a table showing types of storage states of state information. Explanation of symbols of main parts ■...Memory circuit 4...Addition circuit 5...Divided address holding circuit 6...Comparison circuit 7...・Selection circuit

Claims (1)

[Claims] (1) A state information history circuit having a storage means for sequentially storing state information indicating the state of the information processing device, which stores state information necessary for analyzing the error in response to the occurrence of an error in the information processing device. A state information history circuit characterized in that it has a writing means for writing the state information in an area other than the area of the storage means in which the state information has been written.