JPH04287241A - History information storage device - Google Patents

Abstract

PURPOSE:To perform effective address tracing by recognizing the existence of a branch instruction by using the difference in address between the current instruction and its preceding instruction. CONSTITUTION:A data latch circuit 1 fetches the address of an instruction from an address bus 100. The circuit 1 can hold the addresses of two instructions and a data comparator circuit 2 detects the difference in address between the current instruction and its preceding instruction held by the circuit 1. It is indicated that no branch instruction exists when the address of the currently processed instruction coincides with that of the preceding instruction and a branch instruction exists in the address increasing direction when the current address is larger. When the current address is smaller, it is indicated that the branch instruction exists in the address decreasing direction. By detecting the branch instruction in such way and deleting a loop section by discriminating the existence of the loop, effective address tracing is performed with a less amount of hardware and address analysis is also easily performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a history information storage device for an information processing device, and more particularly to a history information storage device with an improved instruction execution address tracing system.

0002

2. Description of the Related Art In the conventional address tracing method, all instruction word addresses are recorded in a trace memory.

0003

In the conventional method described above, all addresses are recorded on a trace memory in order to view all addresses. This method allows you to know the order of addresses in detail, but the amount of data is large and does not fit into memory. Generally when using address trace,
Since the trace contents are viewed in parallel while referring to the program list, there is no need to record all addresses as trace contents, and it is better to delete loops that require a large amount of memory. To put it in an extreme, if only the branch part is recorded, then it is easy to analyze the processing order of the instruction words by referring to a list or the like.

0004

[Means for Solving the Problems] The present invention provides a history information storage device that stores an instruction execution history of an information processing device whose operation is controlled by executing instructions stored in a control storage device. The address of the instruction word in
a first address holding means for holding an address as an address; a second address holding means for holding an address of an instruction word one instruction before the instruction word currently being processed as a second address; and an address comparison means for detecting the difference between both addresses, and if the difference between the addresses detected by the address comparison means and the preset address difference do not match, it is determined that there is a branch instruction at the second address. a branch instruction detecting means for determining the branch instruction; and a first branch instruction detecting means for holding the first address as a first branch destination address.
A branch destination address holding means, a first branch source address holding means that holds the second address as a first branch source address, and an instruction from the branch instruction detection means to determine the branch destination at the time of the previous branch instruction detection. a second branch destination address holding means for holding an address; a second branch source address holding means for holding a branch source address at the time of the previous branch instruction detection according to an instruction from the branch instruction detection means; branch destination address comparison means for comparing the address and the second branch destination address;
A branch source address comparing means for comparing the branch source address with the branch source address, and the branch destination address comparing means and the branch source address comparing means determine that the first branch destination address and the second branch destination address match, and If the first branch source address and the second branch source address match, an instruction loop detecting means (4) determines that instruction execution is looped during this period; instruction address history storage means that takes in a second address and stores the history of the second address up to the present; and in the address history storage means, according to an instruction from the instruction loop detection means,
The present invention is characterized by comprising address write inhibiting means (43) for inhibiting storage of the second address belonging to the instruction loop.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment of the present invention. The operation of this history information storage device will be briefly explained with reference to FIG.

Address bus 100 contains addresses of instructions to be processed by the processing device to which this embodiment belongs. The address of the instruction is taken into the data latch circuit 1 from the address bus 100. The data latch circuit 1 can hold addresses for two instructions. The contents of the register, which is the central part of this circuit, are updated by the instruction data acquisition clock of the processing device. The data comparison circuit 2 compares the address of the currently processed instruction held in the data latch circuit 1 with the address of the instruction one instruction before, and detects the difference between the two addresses. Let X be the address difference in instruction processing when there is no branch instruction,
If the instruction address currently being processed is the first address and the instruction address one instruction before is the second address, then (first address) - (second address) = X, there is no branch due to a branch instruction here. It happens. Also, if (first address) - (second address)>X,
This indicates that there is a branch instruction to the next address (in the direction in which the address increases). In other words, the second address is the branch source address, and the first address is the branch destination address. Also, if (first address) - (second address) <X,
This indicates that there is a branch instruction to the previous address (in the direction in which the address decreases). In other words, the second address is the branch source address, and the first address is the branch destination address.

[0007] These branch source address and branch destination address are defined as the first branch source address and the first branch destination address, and the branch source address and branch destination address at the time of this previous branch instruction detection are defined as the second branch source address and the second branch destination address. It is held by the branch address holding circuit 5 as a branch destination address. The branch data comparison circuit 6 compares the first branch source address and the second branch source address held by the branch address holding circuit 5, and also compares the first branch destination address and the second branch destination address. If both match, it is determined that there is a loop between the first branch source address and the second branch source address, and the address trace data existing between them is erased.

If the data compared by the data comparison circuit 2 is other than a branch instruction or a branch destination address,
The address data is directly sent from the data latch circuit 1 to the data temporary store circuit 3. If data comparison circuit 2
When a branch instruction is found, in addition to the above operations, the branch address holding circuit 5 holds the first address and second address at that time as the first branch destination address and the first branch source address. On the other hand, in the data temporary store circuit 3, when a branch instruction is discovered by the data comparison circuit 2,
Counting of the number of data that has entered the data temporary store circuit 3 is stopped, and the count data is recorded in a built-in register. It then starts counting again and continues counting until the next branch instruction is received. Therefore, the value of the count data is the number of address trace data from one branch instruction to the next branch instruction. In the branch data comparison circuit 6,
Two consecutive branch instruction source addresses and branch destination addresses are compared, and if they are equal, the address trace data between the two branch instructions is regarded as loop data, and an erase signal is output to the data temporary store circuit 3.

The counter register of the data temporary store circuit 3 has a bit indicating whether counting is valid or invalid.
If enabled, the data clock according to the number of counters,
The data is sent to the built-in FIFO and tracer memory 4, and the data in the FIFO is sent to the tracer memory. When the count in the counter register of the store circuit 3 is invalid, that is, when a data erase command is input from the branch data comparison circuit 6, a data clock corresponding to the count number is sent to the FIFO, but the data clock is sent to the tracer main memory 4. does not send out a data clock. Therefore, the data for this count (data for the loop) will be erased.

Next, the operation of each circuit will be explained in detail. The data latch circuit 1 is shown in FIG. The instruction address on the address bus 100 is taken into the data register 11 by the instruction latch clock signal. When the next instruction latch clock signal arrives, the instruction address in the data register 11 is shifted to the data register 12. Then, a new address bus 100 is added to the data register 11.
Read the instruction address. This behavior causes
The data register 11 holds the address of the instruction word currently being processed, and the data register 12 holds the address of one instruction before.

The output from data register 11 is sent to data register 12, data comparison circuit 2, and branch address holding circuit 5.

The data comparison circuit 2 is shown in FIG. The first address and second address from the data latch circuit 1 are compared by comparators 21 and 23, and the comparison result is sent to one-shot multivibrators 24 and 25. Signals from the multivibrators 24 and 25 are sent to the branch address holding circuit 5 and data temporary storage circuit 3 as forward branch signals and backward branch signals, respectively. The circuit 22 of FIG.
A fixed value X is output, and the value of X is the address increment during normal instruction execution (excluding branch instructions). Therefore, if the value of Z in the comparator 23 is 0, this indicates that the difference between the first address and the second address is a normal increase, that is, it is not a branch instruction.

FIG. 4 shows the data temporary store circuit 3. Address trace data input from the data latch circuit 1 is input to the FIFO 31. The instruction latch clock from the processing device is used as the input clock. In addition, in the counter 32, F
The number of address trace data input to the IFO 31 is counted. This count is the counter value register 33
held by. Further, a bit indicating whether the count value is valid or invalid is added to the counter value register 33, and this data causes the data output clock generation circuit 34 to generate a clock for the count value when the count value is valid. Output to FIFO 31 and tracer main memory 5. If disabled, the clock for the count value is
Output to FO31 only. This operation causes FIFO3
This has the same effect as erasing the invalid data contained in 1.

A data erase signal for determining validity/invalidity of the count value is output from the branch data comparison circuit 6.

The branch address holding circuit 5 is shown in FIG. In this circuit, data from a data latch circuit 1 is taken into a register by a forward branch signal and a backward branch signal from a data comparison circuit 2. Branch registers 31 and 32 hold a first branch source address and a second branch source address, and jump destination registers 33 and 34 hold a first branch destination address and a second branch destination address. The contents of registers 31 and 33 are shifted to registers 32 and 34, respectively, when the next forward and backward branch signals arrive.

The address data held by the branch address holding circuit 5 is sent to the branch data comparison circuit 6 shown in FIG. 6 and compared. Compare the first branch source address and the second branch source address, and compare the first branch destination address and the second branch source address.
The branch destination addresses are compared, and comparators 41 and 42 determine whether they match. If both match, the gate circuit 43 generates a data erase signal. A match indicates that there is a branch instruction at the same location and the branch destination address is also the same, so a loop is formed in this part.

As an example, the instruction address is shown in FIG.
), the values of each register will be as shown in FIGS. 7(b) and (c).

Initially, instruction addresses up to 103 are entered into the FIFO as shown in the upper left corner of FIG. At this point, the branch address register contains a value like the one in the middle of the left end, and it is recognized that 103 is a branch instruction. As a result, data 100 to 103 that had been accumulated in the FIFO until then are output to the tracer main memory section. Data starting from the branch destination instruction address 105 is stored in the FIFO. When data 106 is entered into the FIFO, 106 and 110 are entered in the branch address register, so that it is recognized that 106 is a branch instruction. Here, the previous branch instruction address and the branch destination instruction address are compared, and if they do not match, the valid/invalid bit is made valid. The left and right parts in FIG. 7 are loop commands (110 to 11
2) is input. Since the first branch instruction (loop instruction) is compared with the previous branch instructions 106 and 112, they do not match, the valid/invalid bit becomes valid, and F
The data (110-112) in the IFO is sent to the tracer main memory section. When a branch instruction comes for the second time, it is valid because it is a loop instruction and it matches the previous branch instruction.
The invalid bit becomes invalid and the data in the FIFO is not sent to the tracer main memory. The same thing happens the next time the same loop instruction comes. In other words, in the case of a loop, only the address of one loop is held, and the remaining loops are eliminated. FIG. 9 shows which parts are erased (deleted) in actual processing. In order to discover loops using the method described above, trace data is stored from before entering the loop to the part of the loop where the branch source address is located, and is then erased (deleted) at the point where the final branch destination address is located. ) to be done.

[0019]

[Effects of the Invention] As explained above, in the present invention, by detecting a branch instruction, determining the existence of a loop, and deleting the loop portion, effective address tracing can be performed with a small amount of hardware. is possible. Address tracing can be performed for a longer time than conventional tracing with the same amount of memory, and there is no waste in the trace memory, making analysis easier.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a data latch circuit in FIG. 1;

FIG. 3 is a configuration diagram of a data comparison circuit in FIG. 1;

FIG. 4 is a configuration diagram of a data temporary store circuit in FIG. 1;

FIG. 5 is a configuration diagram of a branch address holding circuit in FIG. 1;

FIG. 6 is a configuration diagram of a branch data comparison circuit in FIG. 1;

7 is a diagram showing contents of registers of the address bus and data latch circuit in FIG. 1; FIG.

FIG. 8 is a flowchart showing operations centered on the data temporary store circuit in FIG. 1;

FIG. 9 is a diagram showing a display of loop portions that are deleted in the embodiment of FIG. 1;

[Explanation of symbols]

1 Data latch circuit 2 Data comparison circuit 3. Temporary data store circuit 4 Tracer main memory 5 Branch address holding circuit 6 Branch data comparison circuit 11 Data register 12 Data register 43 Gate circuit

Claims (1)

[Claims] Claim 1: In a history information storage device that stores an instruction execution history of an information processing device whose operation is controlled by executing instructions stored in a control storage device, the address of the instruction word currently being processed is stored as the a first address holding means for holding the address of an instruction word one instruction before the instruction word currently being processed as a second address; and the first address and the second address. and an address comparing means for detecting a difference between both addresses, and if the address difference detected by the address comparing means does not match a preset address difference, there is a branch instruction at the second address. a branch instruction detection means for determining that the first address is a first branch destination address; a first branch destination address holding means for holding the first address as a first branch destination address;
a first branch source address holding means for holding, and a second branch destination address holding means for holding the address of the branch destination at the time of the previous branch instruction detection according to an instruction from the branch instruction detection means;
A second branch source address holding unit that holds the branch source address at the time of the previous branch instruction detection, and a branch that compares the first branch destination address and the second branch destination address according to an instruction from the branch instruction detection unit. The first branch address comparison means, the branch source address comparison means that compares the first branch source address and the second branch source address, and the branch destination address comparison means and the branch source address comparison means, If the destination address and the second branch destination address match, and the first branch source address and the second branch source address match, the instruction loop determines that instruction execution is looped between them. - captures a second address from the second address holding means and the second address holding means;
An instruction address history storage means for storing a history of addresses; and an address write inhibiting means for inhibiting storage of a second address belonging to an instruction loop in the address history storage means according to an instruction from the instruction loop detection means. A history information storage device characterized by: