JPS61131132A - Tracer circuit - Google Patents

Abstract

PURPOSE:To attain accurate trace of data history even when the capacity of a storage circuit is small by counting number of same consecutive data of a trace input data at a counter circuit, writing a count to the storage circuit together with the 1st data. CONSTITUTION:When a consecutive data is inputted as an input data signal 102, a positive output 105 of a comparison coincidence detection circuit 4 is logical 1 and a negative output 106 is logical 0. Thus, an output 107 of an AND circuit 5 is logical 0, an output 104 of an input register 2 is not written in a storage circuit 3 and the value of an address register circuit 9 is unchanged. A negative output 116 of a logical circuit 11 is logical 1 at the same time, the counter circuit 10 is incremented by 1 and when the same consecutive data is intermittent, the output 104 of the register 2 and an output 114 of the counter circuit 10 are written in the storage circuit 3 at the same time. While the same consecutive data continues, the operation is kept, the value of the circuit 9 is unchanged, the counter circuit 10 continues increment of 1 and no data is written to a temporary storage circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Application The present invention relates to a tracer circuit in a data processing device.

BACKGROUND OF THE INVENTION Conventionally, when a trace start signal becomes active, the tracer circuit directly inputs the input signals to be traced to a storage circuit and stores them in the order in which they are input. This method has the disadvantage that a large capacity storage circuit is required to store the desired trace data, and the amount of hardware increases and becomes expensive.

In addition, in order to reduce the amount of hardware, there is a method that stores only the first data when the same data is input continuously, and does not store the next data to be input in the memory circuit. The drawback was that it was not possible to detect how many times the data continued.

Problems to be Solved by the Invention The purpose of the present invention is to solve the above-mentioned drawbacks, namely, that a large-capacity storage circuit is required to store trace data, and to eliminate accurate data if the same continuous data is omitted. It is an object of the present invention to provide a tracer circuit which solves the problem of inability to detect the tracer circuit. a register circuit 2 connected to the register circuit 2, a comparison circuit that compares the outputs of these register circuits 1 and 2, a counting circuit that counts the same continuous data when it is present, and a memory that stores the outputs of the register circuit 2 and the counting circuit. a trace address register circuit that supplies an address to this memory circuit, and a control circuit that writes only the first data to the memory circuit when the same continuous data is detected, and prohibits subsequent merging of the same data. The configuration is adopted. .

Operation Since the present invention is constructed as described above, the input data to be traced is input to the memory circuit through the register circuits 1 and 2t, but the comparator circuit compares the outputs of the register circuits 1 and 2 and detects that they are the same data. In this case, the control circuit prohibits the data from being committed to the storage circuit, the counting circuit counts the number of identical consecutive data, and writes the counted value together with the first data to the storage circuit.

Therefore, accurate data history can be traced even if the capacity of the storage circuit is small.

Example Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1, which shows a block diagram of an exemplary embodiment of the present invention, the tracer circuit of the present invention includes an input register circuit l;
An input register circuit 2, a memory circuit 3, a comparison match detection circuit 4, an AND circuit 5 as a control circuit for controlling write information in the memory circuit 3, and a counting circuit 10.
an AND circuit 6 for controlling the count signal of , an AND circuit 11 that controls the counting of the address register circuit 9, and an output data register circuit 12 that stores the output data of the memory circuit 3.

The clock signal 100 is input to the trace start instruction 7, the lip-flop circuit 7, the AND circuits 6 and 11, the input register circuit 1, the input register circuit 2, the counting circuit 10, the address register circuit 9, and the output data register circuit 12, and outputs the input data signal. 102 is input to the input register circuit 1, the output signal 103 of the input register circuit 1 is compared with the input register circuit 2 and input to the detection circuit 4, and the output signal 104 of the input register circuit 2 is compared with the memory circuit M3 to detect a match. The positive output signal 105 of the comparison match detection circuit 4 is input to the AND circuit 4, and the negative output signal 106 is input to the AND circuit 5 and the AND circuit 11, and the output of the AND circuit 5 is input to the AND circuit 5. The signal 107 is input to the memory circuit 3, the output signal 108 of the AND circuit 6 is input to the counting circuit 10, and the input signal 109
is input to the inverter 8 and the trace start instruction clip 70 tube circuit 7, and the friend input signal 110 is also input to the trace start instruction clip 70 tube flow 21 circuit 7, and the inverter 8
The output signal 111 of is input to the address register circuit 9 and the counting circuit 10, the output signal 112 of the trace start instruction flip-flop circuit 7 is input to the AND circuits 5 and 6,
The output signal 113 of the address register circuit 9 is the memory circuit 3
The output signal 114 of the counting circuit 10 is also input to the memory circuit 3.
The positive output signal 115 of the AND circuit 110 is input to the address register circuit 9, the negative output signal 116 is input to the counting circuit 10, and the output signal 117 of the memory circuit 3 is input to the output data register circuit 12. , the output signal 118 of the output data register circuit 12 is processed as trace data via another logic circuit, and the output signal 118 of the output data register circuit 12 is processed as trace data.
1 is input to the AND circuit 5.

Next, the operation will be explained with reference to the block diagram of FIG. 1 and the timing chart of FIG. 2. First, the trace start instruction flip-flop circuit 7 becomes active and the output signal 11
2 is 111, the input data signal 102 is passed through the input register circuit 1 and the input register circuit 2 to output the output signal 103.2 of both register circuits. lQ4 is input to the comparison match detection circuit, and when the comparison does not match, the negative output signal 1
06 becomes 111), the input data are interpreted as not being the same data, and the output signal 104 of the input register circuit 2 is written into the storage circuit 3. At the same time, +1 is added to the address register circuit 9. At that time, the counting circuit 10 does not operate. However, when the same continuous data is input to the input data signal 102, the positive output signal 105 of the comparison match detection circuit 40 becomes as follows.

01'', the negative output signal 106 becomes 'O'.

When the negative output signal 106 becomes MOm, the output signal 107 of the AND circuit 5 becomes 10, and the output signal 104 of the human register circuit 20 is not written into the memory circuit 3. The output signal 115 of the AND circuit 11 which outputs the +1 addition signal of the address register circuit 9 becomes 101, and the value of the address register circuit 9 does not change. At the same time, the negative output signal 116 of the logic circuit 11 becomes 111, and the counting circuit l
+1 is added to O. The counting circuit 10 has a compensation circuit that counts how many times the same continuous data continues. When the same continuous data is interrupted, the output signal 104 of the input data register circuit 2 and the output signal 114 of the counting circuit 10
are convoluted into the memory circuit 3 at the same time. As long as the same continuous data continues, the above operations continue, the address register circuit 90 value does not change, and the counting circuit continues the +1 operation.
Further, no data is written to the temporary storage circuit 3.

When the same continuous data ends, the positive output signal 105 of the comparison match detection circuit 4 becomes 101, and the negative output signal 106 becomes 101.
changes to 11', and a write operation is performed in the memory circuit 3.

The written trace data is stored in read mode.
One output data register circuit 12Km is outputted, and the output signal 118 of the output data register circuit 12 is sent as trace data and output.

In this way, when the same continuous data is input, by storing the data of -[ only 7 and simultaneously storing the consecutive number of times together with the data, the data is stored in the memory circuit 3 only when the input data changes. By simultaneously writing the results of counting successive circuits in the counting circuit 10 into the memory circuit 3), it is possible to increase the number of memory cycles without impairing the original trace function. It has the advantage of being able to be used effectively and being inexpensive.

Effects of the Invention As explained above, according to the present invention, when the input data to be traced is the same continuous data, only 1 is written into the memory circuit, and the number of consecutive times is counted at the same time, and the value is also recorded at the same time. This makes it possible to effectively utilize the memory circuit without impairing the original trace function, and has the effect of providing an inexpensive trace circuit.

[Brief explanation of drawings]

Figure 1 is a basic block diagram of an embodiment of the present invention, and Figure 2 is a basic timing chart diagram of an embodiment of the present invention. 1... Input register circuit, 2... Input register circuit, 3... Memory circuit, 4...
・Comparison (match detection) circuit, 5......AND circuit,
6...AND circuit, 7...Trace start instruction clip 70 block, 8...NOT circuit, 9...Address register circuit, 10...
...Counting circuit, 11 ...--Logic AND circuit, 12
...Output data register circuit, 100...
...Clock signal, 101...Write signal, 1
02...Input data signal.

Claims (1)

[Claims] a register circuit 1 that stores input data to be traced;
a register circuit 2 connected to the register circuit 1; a comparison circuit that compares the outputs of the register circuit 1 and the register circuit 2; a memory circuit that stores the output of the register circuit 2; and the memory circuit supplies an address. In a tracer circuit having a trace address register circuit and a control circuit that prohibits writing to the storage circuit when the same continuous data is detected by the comparison circuit, the number of times when the comparison circuit detects the same continuous data What is claimed is: 1. A tracer circuit comprising: a counting circuit for counting , and after writing initial data into said memory circuit, the counting output of said counting circuit is stored in said memory circuit.