JPH0261721A - Buffer memory controller - Google Patents

Abstract

PURPOSE:To optimize the data storage quantity by setting the data storage volume in a buffer memory in accordance with the time of data transfer from a first storage means to the buffer memory and that from the buffer memory to a second storage means. CONSTITUTION:A control circuit 9 switches switching circuits 7 and 8 to sides of a write address generating circuit 5 and a data recorder 2 respectively and reads out M-byte data from the data recorder 2 and writes it in a buffer memory 1. At this time, a timer circuit 11 measures the time required for transfer of M-byte data to the buffer memory 1. Next, it measures the time required for transfer from the buffer memory 1 to a host computer 3. These times are compared with each other to set the data storage volume of the buffer memory 1. Hereafter, each time data in the buffer memory 1 reaches the set data storage volume, the control circuit 9 transfers data to the host computer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is directed to control of a buffer memory that efficiently controls a buffer memory provided between a data recording device such as a magnetic disk device or a magnetic tape device and a host computer. Regarding equipment.

[Prior Art] Generally, data transfer between a data recording device such as a magnetic tape device or a magnetic disk device and a host computer is performed via a buffer memory.

This is because the data transfer rate of the data recording device and the data transfer rate of the host computer may be different, or the host computer may be connected to other equipment other than the data recording device.

FIG. 2 is a block diagram of a conventional system that transfers data via a buffer memory. In FIG. 2, 1 is a buffer memory, 2 is a data recording device such as a magnetic disk,
3 is a host computer, and 4 is an interface bus between the buffer memory 1 and the host computer 3.

The buffer memory 1 is of a so-called ring buffer type. In this ring buffer method, the data read from the data recording device 2 is sequentially written into the buffer memory 1 from the first address, and the data written to the buffer memory 1 is written to the interface bus 4 in the order in which it was written to the buffer memory 1. The configuration is such that the data is transferred to the host computer 3 via the host computer 3. In this case, when data is written to the last address of the buffer memory 1, data is written again in order from the first address of the buffer memory 1. However, when the data written in the buffer memory 1 has not been transferred to the host computer 3, it is necessary to stop the operation of writing data from the data recording device 2 to the buffer memory 1.

Note that the operation of writing data to the buffer memory 1 and the operation of reading data from the buffer memory 1 to the host computer 3 are apparently performed simultaneously.

As the interface bus 4 between the buffer memory 1 and the host computer 3, for example, ANSI-8C8I (Sma
ll CoIIputer 5ystelIIInter
race) is used. This interface bus 4 can be logically connected and released between the host computer 3 and the buffer memory 1, and can be released as necessary so that other devices can occupy it even before data transfer is completed. It has become.

[Problems to be Solved by the Invention] By the way, when data read from the data recording device 2 is transferred to the host computer 3, the data transfer speed from the buffer memory 1 to the host computer 3 is higher than that from the data recording device 2 to the buffer. If the data transferred to the buffer memory 1 is transferred to the host computer 3 immediately when the data transfer rate is faster than the data transfer rate to the memory 1, it will match the transfer time between the data recording device 2 and the buffer memory 1.
The host computer 3 always occupies the interface bus 4, reducing the bus efficiency of the entire system.

Therefore, after a certain amount of data read from the data recording device 2 is stored in the buffer memory 1, the host computer 3
In an effort to improve bus efficiency, the data was transferred to the 2nd bus at the same time. That is, at least until a certain amount of data is stored in the buffer memory 1, the interface bus 4 is released from the host computer 3 and the buffer memory 1, improving bus efficiency.

However, the data transfer speed from the buffer memory 1 to the host computer 3 is lower than that from the data recording device 2 to the buffer memory 1.
When the data transfer speed is slower than the data transfer speed, there is a problem that the overall transfer time becomes longer.

The present invention has been made to solve the above problems,
This eliminates the reduction in bus efficiency and deterioration in transfer time caused by the difference in speed ratio between the data transfer speed from the data recording device 2 to the buffer memory 1 and the data transfer speed from the buffer memory 1 to the host computer 3, and eliminates the deterioration of the transfer time under various conditions. In,
It is an object of the present invention to provide a buffer memory control device that can transfer data under the best conditions.

[Means for Solving the Problems] A buffer memory control device according to the present invention detects a first transfer time required to transfer a predetermined number of bytes of data from a first data storage means to a buffer memory. 1st
transfer time detection means for detecting a second transfer time required to transfer data from the buffer memory to the second data storage means; and data storage amount setting means for setting the data storage amount at which data transfer is started from the buffer memory to the second data storage means, depending on the magnitude relationship with the transfer time.

[Function] In the buffer memory control device having the above configuration, the first transfer time detecting means and the second transfer time detecting means are connected to the first transfer time detecting means, respectively.
a first transfer time required to transfer a predetermined number of bytes of data from the data storage means to the buffer memory; and a second transfer time required to transfer the same amount of data from the buffer memory to the second data storage means. When detecting, the data storage amount setting means sets the data storage amount for starting data transfer from the buffer memory to the second data storage means according to the magnitude relationship between the first transfer time and the second transfer time. By doing so, the amount of data accumulated at which data transfer from the buffer memory to the host computer is started is set to an optimum value.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a buffer memory control device according to an embodiment of the present invention. In FIG. 1, ] is a buffer memory that temporarily stores data transferred between the data recording device 2 and the host computer 3, and 5 is a write address that outputs the address when writing data to the buffer memory 1. A generation circuit 6 is an address generation circuit that outputs an address when reading data from the read buffer memory 1, and 7 is an address generation circuit when writing data to the buffer memory 1.
8 is a switching circuit that outputs the address output by the write address generation circuit 5 and the address output from the read address generation circuit 6 to the buffer memory 1 when reading data from the buffer memory 1; A switching circuit 9 switches when transferring data from the buffer memory 1 to the host computer 3; 9 controls writing and reading to the buffer memory 1; controls switching between the switching circuits 7 and 8; Control circuit that counts the amount of data accumulated, IO
11 is a microprocessor that controls the start and stop of data transfer and manages the amount of data stored in the buffer memory 1;
are the buffer memory 1 and the data recording device 2, and the buffer memory 1 and the host computer 3, respectively. This is a timer circuit that measures the time required for data transfer.

Next, the operation of the buffer memory control device shown in FIG. 1 will be explained with reference to the flowcharts in FIGS. 3 and 4. Note that FIG. 3 is a flowchart for setting the data storage amount for starting data transfer to the host computer 3, and FIG. 4 is a flowchart for data transfer based on the set data storage amount.

(1) Steps 81 to S4 The control circuit 9 switches the switching circuits 7 and 8 to the write address generation circuit 5 side and the data recording device 2 side, respectively, and reads M bytes of data from the data recording device 2. The data is transferred to the buffer memory 1 via the switching circuit 8.
(step SL). Note that the data to be written to the buffer memory 1 is, for example, a recording unit of the data recording device 2, which is 128 bytes or 256 bytes.

At this time, the timer circuit 11 calculates the time TDB (SEC) required for M bytes of data to be transferred to the buffer memory 1.
) is measured (step S2).

Next, the control circuit 9 switches the switching circuits 7 and 8 to the read address generation circuit 6 side and the host computer 3 side, respectively, and transfers the M bytes of data stored in the buffer memory 1 to the host computer 3 via the switching circuit 8. (Step S3).

At this time, the timer circuit 11 calculates the time "BH (SEC) required for M bytes of data to be transferred to the host computer 3".
4-1 in total (step 34).

(2) Steps 85 to S9 The microprocessor 9 compares the transfer times measured by the timer circuit 11 (Step 85).

At this time, if the transfer time TBll from the buffer memory 1 to the host computer 3 is longer than the transfer time TDB from the data storage device 2 to the buffer memory 1, the data to be transferred from the buffer memory 1 to the host computer 3 is The storage amount is determined by the minimum transfer unit of buffer memory 1, e.g. 1
Set to byte (step 36). That is, even if the data is 1 byte in the buffer memory 1, it will be transferred to the host computer 3 immediately after the data is transferred.

Further, when the transfer time TBH from the buffer 7 memory 1 to the host computer 3 is shorter than the transfer time "DB" from the data storage device 2 to the buffer memory 1, calculate the transfer speed ratio TBll/TDB (step S7). The table shown in FIG. 5 is referred to based on the calculated transfer speed ratio.

The table shown in FIG. 5 shows the correspondence between the data storage amount of the buffer memory 1 and the transfer speed ratio that optimizes the bus efficiency calculated in advance.

The microprocessor 9 compares the calculated transfer speed ratio with the transfer speed ratio in the table in descending order (step S8).
, when the table transfer rate ratio is smaller than or equal to the calculated transfer rate ratio, the corresponding data storage amount is set (step S9). For example, if the calculated transfer speed ratio is 0.5, the table transfer speed ratio is 0.5.
Set data storage ff11.9N corresponding to 4.

From now on, the control circuit 9 controls the buffer memory 1 every time the data storage amount of the buffer memory 1 reaches the set data storage amount.
The data will be transferred from the host computer 3 to the host computer 3.

(3) Steps 810 to SL4 The control circuit 9 switches the switching circuits 7 and 8 to the write address generation circuit 5 and data recording device 2 sides, respectively, and buffers the data read from the data recording device 2 via the switching circuit 8. While writing to memory 1 (step 81
0), the amount of data written to the buffer memory 1 is counted (step 511).

When the data transfer from the data recording device 2 is completed (step S12), or when the set data storage amount reaches the counted data storage amount, the control circuit 9 controls (
Step S13'), switches the switching circuits 7 and 8 to the read address generation circuit 6 side and the host computer 3 side, respectively, and transfers the data stored in the buffer memory 1 to the host computer 3 via the switching circuit 7 ( Step 514).

(4) Step 815 After transferring the data accumulated in buffer memory 1,
Steps 310 to 814 are repeated until the transfer is completed.

When data transfer from data recording device 2 is completed,
Transfer of data to the host computer 3 is started regardless of the amount of data accumulated in the buffer memory 1.

In this embodiment, the optimal data storage amount corresponding to the transfer speed ratio is shown in a table, but it may be calculated using a formula.

[Effects of the Invention] As explained above, according to the present invention, the data transfer time from the first data storage means to the buffer memory and from the buffer memory to the second data storage means is measured, and according to the measurement results, Since the amount of data accumulated in the buffer memory is set at the time when data transfer starts from the buffer memory to the second storage means, the bus efficiency is good when the transfer speed of the host computer is high, and the transfer speed of the host computer is also high. When the data transfer rate is slow, the effect of obtaining a buffer memory control device that can perform data transfer at a short transfer rate is achieved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a buffer memory control device according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional system that transfers data via a buffer memory, and Fig. 3 is a block diagram of a control device for a buffer memory according to an embodiment of the present invention. FIG. 4 is a flowchart of data transfer according to the set data storage amount, and FIG. 5 is a table showing the optimum data storage amount with respect to the transfer speed ratio. 1... Buffer memory, 2... Data recording device, 3
...Host computer, 5...Write address generation circuit,
6... Read address generation circuit, 7.8... Switching circuit, 9... Control circuit, 10... Microprocessor,
11...Timer circuit. Figure Denita Accumulated Snow 111 Temaru Chi 57! De J difference - Figure 4

Claims (1)

[Claims] The first data storage means and the second data storage means are connected via a buffer memory.
In a control device for a buffer memory that transfers data between data storage means, the first data storage means detects a first transfer time required to transfer a predetermined number of bytes of data from the first data storage means to the buffer memory. a transfer time detection means; a second transfer time detection means for detecting a second transfer time required to transfer the predetermined number of bytes of data from the buffer memory to the second data storage means; and a first transfer time. It is characterized by comprising a data storage amount setting means for setting a data storage amount for starting data transfer from the buffer memory to the second data storage means according to the magnitude relationship between the time and the second transfer time. A control device for buffer memory.