JPH05127831A - Disk controller - Google Patents

Abstract

PURPOSE:To reduce the frequency of generating over run caused by channel response speed delay to occur in a command chain concerning the disk controller. CONSTITUTION:The disk controller to execute transfer preparation at an MPU 12, to operate an automatic data transfer control circuit 9 with the transfer starting instruction of the MPU 12 and to execute data transfer from a disk device to a channel is equipped with a transfer byte counter 11 to be set up by the MPU 12 and to be subtracted each time data are transferred from the disk device after the start of transfer is instructed, auxiliary buffer 17 to store the data transferred from the disk device before the MPU 12 completes the transfer preparation, auxiliary byte counter 15 to count the number of bytes transferred during the relevant period, and comparator circuit 16 to compare the values of both counters 11 and 15, and when the coincidence of the values is shown by the comparison, the data transfer is finished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk controller, and more particularly to a disk controller such as a magnetic disk subsystem used as an external storage device of a large computer system.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional magnetic disk subsystem, FIG. 5 is an illustration of a data format of a magnetic disk track, FIG. 6 is an illustration of command chain processing,
FIG. 7 is a block diagram of the magnetic disk controller.

In the figure, 1 is a host, 2 is a magnetic disk subsystem, 3 is a magnetic disk controller, 4 is a magnetic disk device, 5 is a channel, 6 is a CPU, 7 is a channel interface, 8 is a disk interface, and 9 is a disk interface. An automatic data transfer control circuit, 10 is a transfer buffer, 11 is a transfer byte counter, 12 is an MPU, and 13 and 14 are registers.

Conventionally, in a large computer system, a magnetic disk subsystem as shown in FIG. 4 has been used as an external storage device. The magnetic disk subsystem 2 is composed of a magnetic disk control device 3 and a magnetic disk device 4, and is used by connecting to a host 1.

As shown in the figure, the host 1 is provided with a CPU 6 and a channel 5, and the channel 5 and the magnetic disk controller 3 are connected via a channel interface 7. The magnetic disk control device 3 is also connected to the magnetic disk device 4 via a disk interface 8.

Then, the magnetic disk control device 3 uses the channel 6 and the CPU 6 via the channel interface 7.
Controlled by. Further, the magnetic disk device 4 is controlled by the magnetic disk control device 3 according to the command sent from the channel 5.

In this case, the data transfer performed between the magnetic disk device 4 and the magnetic disk control device 3 and the data transfer performed between the magnetic disk control device 3 and the channel 5 are performed synchronously. The subsystem needs to perform processing called command chain (status report of transfer completion, command reception from channel, preparation for execution of the command) within the gap time (space between fields) of the disk.

As the data format of the disk track in the magnetic disk device 4, for example, a variable length type track format as shown in FIG. 6 is used.

As shown, this data format has a home address HA and a track description record R _0.
, And a plurality of data records R ₁ , R ₂ ... And several variable length records can be recorded in the track.

Further, the track description record R ₀ is made from the count area C and data area D, the data records R _1,
R ₂ ... Includes a count area C, a key area K, and a data area D, respectively.

A gap G is provided between the count area C, the key area K and the data area D. In the gap G, a process called the command chain is performed. A data format in which the key area is omitted is also used.

The command chain process is a process of reporting the execution result of the received command to the channel and receiving the next command to be executed from the channel. In the case of the magnetic disk controller, the command chain process must be completed within the gap time of the field recorded on the magnetic disk (corresponding to the gap G in FIG. 5).

If the command chain processing is not completed within the gap time, the command is executed again after waiting for one rotation of the magnetic disk as an overrun. In this case, the time required for the command chain processing will increase according to the length of the connecting cable between the channel and the magnetic disk controller.

A specific example of the command chain process will be described below with reference to FIG. In this example, the case where there is a data area (DATA) next to the count area (COUNT) is shown, and a gap G is provided before and after the count area and the data area.

When the magnetic disk is rotating, the time taken for the gap G to pass through the magnetic head is shown in FIG.
It becomes the gap time. Then, the command chain process is performed within this gap time.

For example, in the gap time on the front side of the count area (COUNT), a command (SEARC) is issued from the channel.
H ID) is transmitted. This command is received by the magnetic disk control device, a read command is issued to the magnetic disk device, a command reception response is sent to the channel, and further data transfer preparation is performed.

Upon receiving the read command, the magnetic disk device reads the data in the count area and sends the data to the magnetic disk controller. The magnetic disk controller receives the data and sends a data request to the channel.

After that, in the magnetic disk control device, when the transmission data from the channel is received, it is compared with the data and the comparison result is transmitted to the channel. On the channel, when it receives the compare result, it responds to it,
Instruct the command chain.

Then, a command (READ
DATA) is transmitted. In the magnetic disk controller,
When the command (READ DATA) is received, a read command is issued to the magnetic disk device. next,
It sends a command response to the channel and prepares for data transfer.

The processing from the above-mentioned compare result sending processing to the reception of the above command (READ DATA) is the command chain processing time. After that, in the magnetic disk device that receives the read command, the data area (DAT
The data of A) is read and the data is transmitted.

The magnetic disk control device receiving this data automatically sends the received data to the channel under the control of the automatic data transfer control circuit. The same process is repeated thereafter.

Next, a conventional magnetic disk controller will be described with reference to FIG. As shown in FIG. 7, the magnetic disk control device 3 is provided with registers 13 and 14, an automatic data transfer circuit 9, a transfer buffer 10, a transfer byte counter 11, and an MPU 12.

The register 13 is a register for transmitting and receiving control information (control signal, control data, etc.) between the channel 5 and the magnetic disk controller 3, and the register 14 is the magnetic disk device 4 and the magnetic disk. Control device 3
It is a register for transmitting and receiving control information to and from.

The transfer buffer 10 is a buffer used when data is transferred between the channel 5 and the magnetic disk device 4, and the automatic data transfer circuit 9 transfers the data via the transfer buffer 10. Is a circuit that automatically performs.

The transfer byte counter 11 indicates the number of bytes of the data transferred by the automatic data transfer circuit 9. The value is set from the MPU 12 before the transfer is started, and is decremented each time the data is transferred. It is something. Normally, when the value indicates 0, the data transfer is completed.

In the magnetic disk controller 3 having the above structure, for example, when the command chain process shown in FIG. 6 is performed to transfer data from the magnetic disk device to the channel, the process is performed as follows.

First, in the magnetic disk controller 3, the MP
U12 uses the register 13 to execute the command chain. At this time, the MPU 12 that received the channel command
Then, via the register 14, to the magnetic disk device 4,
Issue a read command to read data.

After that, the MPU 12 sets up the automatic data transfer control circuit 9 and prepares for data transfer.
The transfer byte counter 11 is set up (the number of transfer bytes is set), and the data transfer start is instructed.

Then, the data read by the magnetic disk device 4 is transferred to the channel 5 by performing data transfer by the automatic data transfer circuit 9.

The above data transfer will be described in more detail as follows. If a command for reading data is issued from the magnetic disk controller 3 to the magnetic disk device 4, the magnetic disk device 4 reads out predetermined data from the disk based on the command.

Thereafter, the magnetic disk device 4 sends a DATA sending signal to the magnetic disk control device 3 and transfers the read data. In the magnetic disk controller 3, after storing the transfer data in the transfer buffer 10, the automatic data transfer circuit 9 causes the channel 5
Transfer data to.

At this time, in the automatic data transfer circuit 9, each time the DATA transmission signal from the magnetic disk device is received,
Transfer byte counter 11 for the number of bytes of transferred data
When the count value of the transfer byte counter 11 becomes 0, the data transfer is stopped.

At the start of data transfer, the MPU 12
Thus, when the data in the transfer buffer 10 is transferred to the channel 5 by the number of bytes set in the transfer byte counter 11, the automatic data transfer circuit 9 stops the data transfer.

Data is transferred from the magnetic disk device to the channel as described above, but it is assumed that the command issuance is delayed and the command chain time is extended depending on the channel state. In such a case, the data read by the magnetic disk device may be transferred before the automatic data transfer control circuit 9 is activated because the MPU 12 is not ready for data transfer.

In this case, the automatic data transfer control circuit 9 cannot receive the transferred data. Therefore, in the magnetic disk control device, as a data overrun,
In order to execute the command again, the command retry status is reported to the channel, and after the disk makes one revolution,
Execute the same command again.

[0036]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. (1) The process called the command chain needs to be performed within the time of the gap G of the data format in the disc track. However, in the magnetic disk subsystem used in recent large computer systems,
An optical interface has been put to practical use as a channel interface, and its connection distance has become long.

Therefore, the channel response time during execution of the command chain tends to be delayed. Further, in the magnetic disk device, since the gap length tends to be shortened in order to increase the disk capacity, the current data synchronous transfer is
It is already reaching the limit.

In such a situation, a delay in the processing speed caused by the channel state leads to an increase in the command chain time, which results in overrun detection of the magnetic disk controller.

(2) When data is read from the magnetic disk device and transferred to the channel, the magnetic disk control device prepares for data transfer if the arrival of a command from the channel is delayed during the execution of the command chain. There is a situation in which the data sent from the magnetic disk device cannot be received because the processing by the MPU) is not in time.

In such a case, the magnetic disk control device reports the command retry status to the channel in order to execute the command again as an overrun. Then, after the disk has rotated once, the same command is executed again. Therefore, the processing is performed after the disk makes one rotation, so that the processing speed of the CPU of the host decreases.

(3) If the response speed of the channel becomes slow during the execution of the command chain, the frequency of occurrence of data overrun or command overrun becomes high. As a result, the processing speed of the CPU on the host side becomes slow.

An object of the present invention is to solve such a conventional problem and to reduce the frequency of occurrence of data overrun due to the delay in the response speed of the channel occurring during the command chain.

[0043]

FIG. 1 is a principle view of the present invention, in which the same reference numerals as those in FIGS. 4 and 7 indicate the same elements.
Further, 15 is an auxiliary byte counter, 16 is a comparison circuit, 1
Reference numeral 7 indicates an auxiliary buffer, and 18 indicates an AND gate.

In order to solve the above problems, the present invention has the following configuration. That is, at least an MPU (processor) 12 that performs various controls and an automatic data transfer control circuit 9 that automatically transfers data from a disk device to a channel according to an instruction from the MPU 12 are provided.
After the data transfer preparation by the MPU 12 is performed, the automatic data transfer control circuit 9 is operated by the transfer start instruction from the MPU 12, and the disk controller that executes the data transfer from the disk device to the channel is set up from the MPU 12 and After the transfer start instruction is sent, the transfer byte counter 11 that subtracts the number of bytes each time data is transferred from the disk device, and an auxiliary device that stores the data transferred from the disk device before the MPU 12 completes the data transfer preparation Buffer 17 and auxiliary byte counter 15 that counts the number of bytes of data transferred during the period
And a comparison circuit 16 that compares the values of the transfer byte counter 11 and the auxiliary byte counter and validates the output when both counter values match. When the output of the comparison circuit 16 is validated, automatic data transfer control is performed. The data transfer by the circuit 9 is completed.

[0045]

The operation of the present invention based on the above construction will be described with reference to FIG. Under normal conditions, MPU12
Executes the command received from the channel, issues a command to the disk device, sets up the automatic data transfer control circuit 9 and the transfer byte counter 11, and prepares for transfer.

After the transfer preparation is completed, when the MPU 12 activates the automatic data transfer control circuit 9, the data transfer from the disk device to the channel is started. At this time, the data transferred from the disk device is stored in the auxiliary buffer 17, further stored in the transfer buffer 10, and then transferred to the channel.

Transfer byte counter 1 at the time of this data transfer
The count value of 1 is subtracted by the number of bytes of the transferred data. Since the count value of the auxiliary byte counter 15 is 0 during normal data transfer, the data transfer is continued until the count value of the transfer byte counter 11 becomes 0.

However, when the command issuance is delayed and the command chain time is extended due to the state of the channel, M
The PU 12 will not be ready for data transfer in time to receive the data from the disk device. In this case, the transfer data is stored in the auxiliary buffer 17, and the count value of the auxiliary byte counter 15 is stored as the transferred data. Add only the number of bytes.

Then, when the data transfer preparation is completed and the automatic data transfer control circuit 9 is activated, the addition of the auxiliary byte counter 15 is stopped and the transfer byte counter 11 starts the subtraction. Then, the data in the auxiliary buffer 17 is transferred to the channel via the transfer buffer 10.

After that, when the count value of the transfer byte counter 11 and the count value of the auxiliary byte counter 15 become equal, the output of the comparison circuit 16 becomes valid, and the data transfer by the automatic data transfer control circuit 9 ends.

In this way, even if the command chain time is extended, data overrun does not occur and
It is possible to continue the processing as it is. as a result,
No reduction in processing speed occurs.

[0052]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 3 are diagrams showing an embodiment of the present invention, FIG. 2 is a block diagram of a magnetic disk controller, and FIG. 3 is a data transfer processing flowchart.

In the figure, the same reference numerals as those in FIGS. 1, 4 and 7 indicate the same parts. 17A indicates an auxiliary register.

This embodiment is an example applied to a magnetic disk subsystem, and the system configuration is the same as the example shown in FIG. The data format of the tracks on the magnetic disk is also the same as that of the conventional example shown in FIG.

In the magnetic disk subsystem, in this embodiment, the magnetic disk control device is constructed as shown in FIG. 2, and the magnetic disk device is the same as the conventional example.

As shown in FIG. 2, the magnetic disk controller 3 includes registers 13 and 14, an automatic data transfer control circuit 9, a transfer buffer 10, a transfer byte counter 11,
MPU 12, AND gate 18, auxiliary byte counter 1
5, a comparison circuit 16, and an auxiliary register 17A are provided.

Among these, auxiliary register 17A, AND gate 18, auxiliary byte counter 15, comparison circuit 16
Is a structure newly added in this embodiment, but the other structures are the same as those in the conventional example.

The MPU 12 accesses the registers 13 and 14 and the automatic data transfer control circuit 9 to
It is a processor that performs various controls such as data transfer in the magnetic disk controller 3. The register 13 is a register for transmitting and receiving control information between the channel 5 and the magnetic disk controller 3.

The register 14 includes the magnetic disk device 4 and
This is a register for transmitting and receiving control information to and from the magnetic disk controller 3. The automatic data transfer control circuit 9
It is a circuit that controls data transfer between the channel 5 and the magnetic disk device 4.

Auxiliary register 17A and transfer buffer 10
Is for temporarily storing the transfer data controlled by the automatic data transfer control circuit 9. That is, the data to be transferred from the magnetic disk device to the channel is first stored in the auxiliary register 17A and then transferred to the transfer buffer 10.
Again, and the data is transferred from the transfer buffer 10 to the channel.

The transfer byte counter 11 is a counter indicating the number of bytes of data transferred between the magnetic disk controller 3 and the magnetic disk device 4, and its value is set from the MPU 12 before the start of data transfer. The counter is decremented each time data is transferred.

The auxiliary byte counter 15 is provided in the magnetic disk unit 4 before the MPU 12 completes preparations for data transfer.
When data is transferred from, the counter is a counter that adds the number of transfer bytes until the completion of transfer preparation and counts the number of bytes. Normally, the value is set to 0.

The comparison circuit 16 uses the transfer byte counter 11
Of the auxiliary byte counter 15, and outputs a valid signal (for example, "1") when both count values are equal as a result of the comparison.

An AND gate (AND) 18 outputs the output signal a of the automatic data transfer control circuit 9 and the magnetic disk device 4
The DATA sending signal b from the above is used as an input signal, and its output is sent to the auxiliary byte counter 15.

In this case, the signal a is a = 0 when the automatic data transfer circuit 9 is operating, and is a when the automatic data transfer circuit 9 is stopped.
= 1. Further, the signal b becomes b = 1 when data is transferred from the magnetic disk device, and normally b = 0.
Has become.

In the AND gate 18, the output signal is 1 only when the input signal is a = b = 1, and the output is 0 otherwise, and the auxiliary byte counter 15 is provided only when the output of the AND gate 18 is 1. Will count up.

That is, in the auxiliary byte counter 15, a
The number of b = 1 when = 1 is counted, but since the signal b matches the number of bytes of transfer data, the signal is transferred from the magnetic disk device while the automatic data transfer control circuit 9 is stopped. The number of bytes of data is the auxiliary byte counter 1
It is counted up at 5.

The operation of the magnetic disk control device based on the above configuration will be described with reference to the data transfer processing flowchart of FIG. The process numbers in FIG. 3 are shown in parentheses.

The operation of this embodiment is processing for transferring the data read from the magnetic disk device to the channel based on the channel command, and operates as follows. The command chain process is the same as that shown in FIG.

In a normal state (a state in which the processing of the command chain is performed without delay), the MPU 12 receives the channel command from the channel via the register 13 (S1), and analyzes the command (S2). ..

Next, the MPU 12 uses the register 14 to issue a command to the magnetic disk device to execute the received command (S3). Next, setup of the automatic data transfer control circuit 9 and transfer byte counter 1
By performing the setup of 1, the data transfer preparation (S5) is performed.

When the data transfer preparation is completed, the MPU 12
Activates the automatic data transfer control circuit 9 to start data transfer from the magnetic disk device to the channel (S6).

Thereafter, the data read by the magnetic disk device is transferred to the magnetic disk control device 3. This transfer data is once stored in the auxiliary register 17A, and the data is transferred to the transfer buffer 10. It In this case, the number of bytes of transfer data is determined by the automatic data transfer circuit 9
Sent to.

At this time, the automatic data transfer control circuit 9 determines from the count value of the transfer byte counter 11 that
The number of bytes of the transferred data is subtracted. Also,
The data stored in the transfer buffer 10 is then transferred to the channel by the automatic data transfer control circuit 9.

In this way, the transfer byte counter 11
The data transfer is continued until the count value of 1 and the count value of the auxiliary byte counter 15 match and the output of the comparison circuit 16 becomes valid (state in which the level becomes "1").

In the normal case, since the count value of the auxiliary byte counter is 0 as described above, the data transfer is continued until the count value of the transfer byte counter 11 becomes 0. When the data transfer is completed (S7), the command execution result is notified to the channel (S8), and if there is a command chain instruction again (S9), the above process is repeated.

However, when the command issuance is delayed and the command chain time is extended due to the channel state, the data transfer preparation cannot be completed in time in the magnetic disk control device and the data from the magnetic disk device is received. Will be done.

In this case, the transferred data is stored in the auxiliary register 17A, and the number of stored bytes is added by the auxiliary byte counter 15. That is, when the data transfer preparation is not in time, the automatic data transfer circuit 9 is not operating and the signal a is a = 1.

When data is stored in the auxiliary register 17A in this state, the signal b becomes b = 1 for the number of bytes, the output of the AND gate 18 becomes 1, and the auxiliary byte counter 15 adds the data as described above. ..

After that, when the data transfer preparation by the MPU 12 is completed and the automatic data transfer control circuit 9 is activated,
Since a = 0, the auxiliary byte counter 15 stops counting. At the same time, the subtraction of the transfer byte counter 11 is started, and the data stored in the auxiliary register 17A is transferred to the transfer buffer 10 and sent to the channel.

This data transfer is continued until the count value of the auxiliary byte counter 15 indicating the number of bytes transferred by the completion of transfer preparation and the count value of the transfer byte counter 11 indicating the number of remaining transfer bytes become equal to each other. Then, the output of the comparison circuit 16 becomes 1 and the data transfer is stopped.

For example, the number of bytes of the data stored in the auxiliary register 17A by the time the transfer preparation is completed is M bytes, and MP
It is assumed that the number of bytes set in the transfer byte counter 11 by the U12 is N bytes (N> M).

In this case, the count value of the auxiliary byte counter 15 is M, and the count value of the transfer byte counter 11 is N at the initial stage of setting. After being activated, the automatic data transfer control circuit 9 automatically transfers data via the transfer buffer 10 and subtracts the count value of the transfer byte counter 11. This subtraction receives a signal from the magnetic disk device. Therefore, the first M bytes carry out only data transfer without subtraction.

Therefore, in order to start the subtraction of the transfer byte counter 11 from the data transfer of the (M + 1) th byte, when the automatic data transfer control circuit 9 transfers the data of N bytes,
The count value of the transfer byte counter 11 becomes M.

At this time, the two count values input to the comparison circuit 16 become M, and both count values match. In this state, the operation of the automatic data transfer control circuit 9 is stopped by the signal output from the comparison circuit 16.

By doing so, even if the issuing of the channel command is delayed due to the channel state and the command chain time is extended, the data sent from the magnetic disk device is stored in the auxiliary register 17A and the auxiliary byte counter 15. Can be received.

After the automatic data transfer control circuit 9 is activated, the data stored in the auxiliary register 17A and the data subsequently sent from the magnetic disk device 4 are transferred to the channel, and the byte set by the MPU 12 is transferred. After transferring a certain number of data, the data transfer can be automatically terminated.

[0088]

As described above, the present invention has the following effects. (1) The delay in response speed caused by the channel condition is
Even if the automatic data transfer control circuit cannot receive the data transferred from the disk device because it affects the time for data transfer preparation in the disk controller, the auxiliary byte counter and auxiliary buffer (or auxiliary register) By performing the data storage process and receiving the data, the data transfer can be performed without any trouble. Therefore, the frequency of occurrence of data overrun is extremely low.

(2) Since the frequency of occurrence of data overrun caused by the delay in the response speed of the channel occurring during the command chain can be improved, the decrease in processing speed is reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a magnetic disk controller according to an embodiment of the present invention.

FIG. 3 is a flowchart of a data transfer process according to the embodiment.

FIG. 4 is a configuration diagram of a conventional magnetic disk subsystem.

FIG. 5 is an explanatory diagram of a data format of a magnetic disk track.

FIG. 6 is an explanatory diagram of command chain processing.

FIG. 7 is a block diagram of a conventional magnetic disk control device.

[Explanation of symbols]

 3A Disk controller 9 Automatic data transfer control circuit 10 Transfer buffer 11 Transfer byte counter 12 MPU (processor) 15 Auxiliary byte counter 16 Comparison circuit 17 Auxiliary buffer 18 AND gate (AND)

Claims (1)

[Claims] 1. A processor comprising at least a processor (12) for performing various controls and an automatic data transfer control circuit (9) for automatically transferring data from a disk device to a channel according to an instruction from the processor, After preparing the data transfer according to (12),
In a disk control device which operates an automatic data transfer control circuit (9) in response to a transfer start instruction from the processor to execute data transfer from a disk device to a channel, the data transfer is set up from the processor (12). After the start instruction, a transfer counter (11) that is subtracted each time data is transferred from the disk device, and an auxiliary device that stores the data transferred from the disk device before the processor (12) completes the data transfer preparation. The values of the buffer (17), the auxiliary counter (15) that counts the number of data transferred during the period, and the value of the transfer counter (11) and the auxiliary counter are compared, and both counter values match. When the output of the comparison circuit (16) becomes effective, the automatic data transfer is provided. Disk control device according to claim by the control circuit (9) that it has to terminate the data transfer.