JPS64729B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for removing defective products such as a 1-chip microcomputer (microcomputer) with a prescaler. It concerns dynamic burn-in, which exposes products to the environment and detects early defective products.

Figure 6 shows the failure rate of a single-chip microcomputer. The figure shows a high failure rate in the early failure area.
is the region with few failures, and is the degraded mode failure region. Before shipping a 1-chip microcomputer, it is necessary to eliminate those that cause early failures.

[Conventional technology]

Conventionally, the following method has been used to eliminate this initial type defect.

State Burn In
BI) Apply bias to the microcontroller under high temperature and leave it for a specified period of time to remove defective products.

Clocked Burn In (Clocked BI)
In addition to biasing the microcontroller under high temperature, the microcomputer is operated with a clock and left to operate for a specified period of time to remove defective products.

Dynamic Burn In
BI) Apply a test pattern to the microcomputer, wait for a predetermined period of time while the microcomputer is operating, and remove defective products.

In the old days, only static BI was performed, for example, by applying only DC power voltage and leaving the product in a high-temperature room at about 125 degrees Celsius for a predetermined period of time to remove defective products. but,
In this case, since the microcomputer is not operating, it is not possible to sufficiently eliminate early-stage failures. recent years,
It has become common practice to perform clocked BI and perform burn-in while operating the microcontroller by supplying CLK, but only a portion of a single-chip microcontroller can be operated by applying a clock. Therefore, it is required to perform dynamic BI to perform even more rigorous burn-in and eliminate things that cause early failures.

[Problem that the invention seeks to solve]

However, today, single-chip microcontrollers have a prescaler (consisting of two flip-flops, for example), which divides CLK to a predetermined frequency and generates a pulse that switches an instruction at that point. However, in order to use a one-chip microcomputer alone, it is not necessary to reset the F/F of the prescaler, so it does not have a reset circuit. Therefore, in the dynamic BI mentioned above,
If you try to operate hundreds of 1-chip microcontrollers by connecting them in a parallel manner, it will become impossible to drive them in a parallel manner because each instruction will be switched at a different position. Therefore, conventionally, when attempting to dynamically burn-in a large number of one-chip microcomputers at the same time, one driver must be connected to each microcomputer, resulting in an increase in burn-in costs.

[Means for solving problems]

In the present invention, the F/F of the prescaler is set to the same state for all samples, so that the F/F of each one-chip microcomputer is set to a predetermined state.
When the command can be switched, the clock supply is stopped, a wait is made, and the process starts when all samples are in the same state. In this way, one driver can commonly supply instructions to operate each sample, and therefore the cost of dynamic BI can be significantly reduced.

〔Example〕

FIG. 1 shows a circuit according to an embodiment of the present invention, and the prescaler synchronization circuit that matches the F/F of the prescaler of one chip microcomputer is composed of two circuits:
In other words, each chip microcontroller test device (DUT)
DUT enable standby circuit 11 required for each DUT enable standby circuit 11,
It is composed of a clock supply/synchronous start circuit 12 common to each DUT 1. The DUT enable standby circuit 11 includes a monomulti 2 and a NAND gate 4,
Consists of 5 and 6. On the other hand, the clock supply/synchronization start circuit 12 is connected to the counter 3 (here 4).
It has a clock (CLK) supply terminal 9, an inverter 7, a NAND gate 8, and a clock (CLK) supply terminal 9.
Clock supply terminal 9 is connected to one terminal of NAND gates 4 and 5, and the most significant bit Q _D of counter 3 is connected to one terminal of NAND gates 4 and 5.
is connected to the other terminal of the NAND gate 4, and the inverted output of the monomulti 2 is connected to the other terminal of the NAND gate 5. The outputs of the NAND gates 4 and 5 are connected to one and the other terminals of the NAND gate 6, and the output of the NAND gate 6 is connected to the Extal terminal of the DUT 1. The E (IUR) terminal of the DUT is connected to input B of mono multi 2. The reset terminal R of the DUT is
Connect to reset switch 10. The clock input terminal CLK of the counter 3 is connected to the clock terminal 9 via a NAND gate 8, and the other terminal of the NAND gate 8 is connected via an inverter 7 to the terminal of the most significant bit _QD of the counter 3. A reset switch 10 is connected to the CL terminal for clearing the contents of the counter 3.

The operation of the circuit is as follows: First, reset switch 10 is turned on to clear counter 3 and mono multi 2 is reset. Q _D of counter 3 is zero (“L”) and the inverted output of mono multi is “H”. be.
Therefore, since the input to the NAND gate 5 is "H" and the input to the NAND gate 4 is "L", the NAND gate 5 is opened and the NAND gate 4 is closed. Therefore, CLK at the clock terminal 9 passes through the NAND gates 5 and 6 and is applied to EXtal of the DUT 1. When the state of the F/F of the prescaler of the DUT becomes available for command switching, the terminal E (IRU) of the DUT changes from "L" to "H" and is input to the input B of the monomulti. Mono multi 2 catches the rising edge and output Q becomes “L” →
“H” becomes “H” → “L”. Therefore,
The input of NAND gate 5 changes to "L" and closes. In this state, both the NAND gates 4 and 5 remain closed, and the supply of the clock CLK to the DUT is stopped.Therefore, the DUT 1 waits with the prescaler F/F in a state where the instruction can be switched.

On the other hand, the most significant bit _QD of counter 3 is “L”
Therefore, since the input of NAND gate 8 is "H" and the gate is open, clock terminal 9 is
CLK is supplied to counter 3 and the count advances.
Then, when the counter fully counts (in this case, 1111 since it is a 4-bit counter), Q _D changes from "L" to "H", and therefore the NAND gate 8
Since the input becomes "L" and the gate is closed, the clock supply is stopped and the counter 3 is kept at full count. Therefore, Q _D is always “H”,
Since the input to the NAND gate 4 becomes "H", the NAND gate 4 opens. That is, all the DUTs in the standby state are started by being supplied with the clock CLK at some point. In the above, the CR time constant of the monomulti 2 must be set larger than the time constant of the E signal input to the B terminal.

Fig. 2 shows a time chart when the prescaler of the above embodiment divides the frequency by 4, and Fig. 1 shows the time chart.
DUT1 F/F in the second cycle of clock CLK
The output from the E (IRU) terminal of DUT1 changes from “L” to “H” in the second cycle of the clock CLK, and the CLK (EXtal) clock stops. Goes into standby mode. Similarly, other DUTs 2, 3, 4, etc. also enter the standby state, for example, at the third, fourth, and first cycles of the illustrated clock.
It will be clear that when the prescaler is divided by 4, it is guaranteed that all DUTs will be in the standby state (all E signals are "H") within 8 cycles of clock CLK. Then, when the most significant bit EQ _D of the counter becomes "1"("H" level), the clock CLK starts being supplied to each DUT, allowing each DUT to start in a synchronized state. . Once the prescaler is synchronized in this way, all that is left is to apply the test pattern from the E-ROM to the other terminals at the same time, and the dynamic
BI becomes possible.

Figures 3 and 4 show the overall configuration for implementing this dynamic BI, and as shown in Figure 3, each DUT1 to i is individually provided with the DUT enable standby circuit 11 shown in Figure 1. A clock supply/synchronous start circuit 12 is commonly connected to these. On the other hand, the other terminals of each DUT1 to i are commonly connected to a line 32 connected to a driver 31 of a test pattern generator 30. FIG. 4 shows a dynamic BI device using the prescaler synchronization circuit shown in FIG.
2. A test pattern generator 30, a driver 31, etc. are arranged, and are connected to a high temperature tank 42 via a joint 43.
(For example, Ta = 125℃). Dynamic BI is performed for 48 to 96 hours, after which the DUT is removed from the high-temperature bath, tested by other means, and the defective 1-chip microcontroller is removed.

Above, the case where the prescaler of the DUT divides the frequency by 4 has been shown as an example, but it is not limited to this, and can be applied to, for example, divide by 6, divide by 12, etc. In that case, as shown in FIG. It is obvious that the number of bits in counter 3 should be increased.

Next, a fifth embodiment of the test pattern generator 30 will be described.
This will be explained using figures. The pattern memory (1) 51 is, for example, a 1920 Kbit EPROM, and patterns for 40 pins are written therein. In order to generate a pattern from this pattern memory (1), a pattern counter 54 for advancing the memory address and a controller (microprocessor) 53 for controlling this are provided as a mechanism for generating addresses.
The pattern memory (1) stores the function pattern to be applied to the DUT {however, the FT Function Pattern excluding RAM and RM (same as the tester pattern)}. ROM, RM
In the case of the test pattern, there are many repetitions, and the pattern length becomes too long in the case of a continuous pattern.
Therefore, for patterns that are difficult to store in memory, such as test patterns for RAM and RM, the controller 53 is configured to function as an algorithmic pattern generator. Therefore, a pattern (2) 52 is provided, and a program (RAM, R
Write the M pattern and the control program for the pattern generator. A pattern memory (2) capacity of 1 Kbyte is sufficient. controller 5
3 reads the program in the pattern memo (2) and uses it to generate instructions. In this case, an 8-bit microcomputer is used as the DUT, so the instructions are for the 8 pins shown. In this way, under the control of the controller 53, the line 6
3 and 62 are supplied with patterns for 40 pins and instructions for 8 pins, respectively.
Controller 53 sends a control signal to multiplexer 55 via line 61 and determines which signal
Switch to send to DUT. In order to provide versatility, it is preferable to perform this switching for all 40 pins, but in this example, it is sufficient to perform this switching for only 8 pins. For the remaining pins, a pattern of line 63 may be provided. When switching the multiplexer for 40 pins, a fixed 0, 1 pattern may be given to the remaining pins.

Next, a case where the counter 56 is used will be explained. The above-mentioned test pattern is generally generated for each well-organized cycle such as an instruction cycle. However, since the required timing differs depending on the DUT pin, it may be better to include a waveform that changes in a specific state of the instruction cycle depending on the pin. In particular, when applying a test pattern to hundreds of DUTs connected in parallel, the applied waveform may become dull, so if the test pattern waveform is applied to the pins at too strict a timing, it may not work. Therefore, the clock CLK is divided by the counter 56, and
Generate timing signals T ₁ to Tm for each state of the instruction cycle, provide a DFF (#1 to 40) corresponding to each pin of the DUT, and output the required timing signal from T ₁ to Tm to its control terminal Tn. Make sure to include the timing. In this way, it is possible to set the timing of applying the test pattern depending on the pin, and it is possible to apply the test pattern waveform to each pin at a timing with some margin.

The control of the pattern counter 54 will be outlined. When the controller 53 is generating an instruction using the pattern memory (2) 52, the controller 53 applies an inhibit signal to the AND gate 57 and closes the AND gate 57. Therefore, since the clock CLK is no longer input to the pattern counter 54, the counter stops and the pattern memory is
(1) can be made stationary. Others, controller 53
sends a reset signal to RST of the pattern counter 54, and when the putter counter 54 finishes counting,
The CARRY terminal is designed to send a termination signal to the controller.

In addition, in the circuit of Fig. 5, the pattern memory
(1), pattern memory (2) is typically RM (PR
It consists of OM, EPRM, E ² RM) and has a structure that can be replaced as necessary. Further, the pattern memory (1) and the pattern memory (2), which is a storage device of the controller, may have an integral structure.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to synchronize the operating states of each type of IC that has an internal clock source and runs on its own, such as a one-chip microcomputer with a prescaler. Therefore, it has become possible to apply a common test pattern to a large number of ICs, operate them, and perform dynamic burn-in, which was previously impossible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a prescaler synchronous circuit according to an embodiment of the present invention, FIG. 2 is a time chart of the prescaler synchronous circuit, FIG. 3 is an overall circuit diagram of an embodiment of the present invention, and FIG. 4 is a diagram of the present invention. FIG. 5 is a layout diagram of an embodiment of the invention, FIG. 5 is a configuration diagram of a test pattern generation section in an embodiment of the invention, and FIG. 6 is a diagram of changes in failure rate over time. (Main codes) 1...DUT, 2...One shot multi, 3...Counter, 4, 5, 6, 8...
...NAND gate, 7...Inverter, 9...Clock terminal, 10...Reset switch, 11...
DUT enable standby circuit, 12... Clock supply/synchronization start circuit, 30... Test pattern generator, 31... Driver, 51... Pattern memory (1), 52... Pattern memory (2), 53...
Controller, 54...Pattern counter, 55
...Multiplexer, 56...Counter, 57...
And gate.

Claims (1)

[Claims] 1. In a dynamic burn-in method in which a test pattern is applied to a plurality of microcomputers equipped with a prescaler, the microcomputers are operated in a high temperature atmosphere, and initial defective products are removed. a circuit provided for each of the computers, which supplies a clock from the clock supply terminal until the state of the prescaler of the microcomputer becomes such that an instruction can be switched, and stops the clock supply in response to an enable signal of the microcomputer; A circuit that starts supplying clocks from the clock supply terminal to the plurality of microcomputers in a state where the prescalers of all the microcomputers can switch instructions, and a test pattern common to other terminals of the plurality of microcomputers. A dynamic burn-in method for a microcomputer with a prescaler, characterized in that the burn-in is performed by synchronizing the states of a plurality of microcomputers. 2. The circuit that commonly provides the test pattern is
a storage device that stores a function pattern to be applied to the microcomputer; a controller that reads a necessary pattern from the storage device and controls the application; an algorithmic pattern generator; 2. A dynamic burn-in method for a microcomputer with a prescaler according to claim 1, further comprising a circuit for selectively outputting a pattern to be read and an algorithmic pattern.