JPS58214908A - Sequence controller - Google Patents

Abstract

PURPOSE:To facilitate an easy sequence controller, by latching for a fixed time the data obtained by designating and reading with a time division access the upper and lower addresses of an ROM which stores control data of plural systems to be controlled with different periods. CONSTITUTION:A sequence controller is provided with an address generator 31, an ROM32 and latch circuits 33-40. The generator 31 generates lower addresses A0-A3 of the ROM32 through a rotary encoder 22 and the 1st counter 23 as well as upper addresses A4-A6 through an oscillator 41 and the 2nd counter 42 respectively. The circuits 33-40 are addressable and designated for their addresses with an address signal Am of the counter 42 and then read in time division output data O1-O8 of the ROM32 and synchronously with a system clock signal of the oscillator 41. Then the circuits 33-40 supply control outputs O1A- OSH to elements to be controlled. Thus it is possible to form a system having flexibility and general-purpose applications.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence control device that sequentially operates a plurality of controlled elements at predetermined timing to execute a predetermined function.

A conventional sequence control device consists of a dedicated sequence control device consisting of A-Dounier logic such as logic gates, registers, and flip-flops, and a central processing unit (OPU).
), an input/output device (VO), and a memory, and there is a general-purpose sequence control device whose control program is determined by software. Among these, dedicated sequence control devices generally lack flexibility and expandability as a system because the hardware cannot be easily changed.

Furthermore, with the recent development of LSI technology, extremely inexpensive OPUs have become available, and general-purpose sequence control devices using computers are now widely put into practical use. However, since this general-purpose sequence control device performs sequence control using a stored program,
Although the system has flexibility and expandability, it tends to lack real-time performance, and it is not easy to design a real-time multitasking program, especially in a system equipped with a large number of VOs. By the way, the software setup d1 of a general-purpose sequence control device by a computer generally includes (1) specification determination, (2) timing chart creation, (5) flowchart creation, (4) coding, (5) debugging, and (6) ) This is done through a complicated process of examining actual equipment.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art by using a read-only memory, an address generator, and a latch circuit, to create a system configuration that is highly flexible and expandable, and that also meets the requirements for real-time performance. We would like to provide a sequence control device that can satisfy the following requirements.

Sequence control configured to store control data for sequentially driving multiple controlled elements at predetermined timing in a read-only memory (hereinafter referred to as ROM) and read out the control data in the ROM at an address specified by an address generator. The device can be used as a sequence control device for completely different purposes by simply changing the control data in the ROM, and is versatile.Moreover, it does not require arithmetic processing by the OPU, so it can satisfy real-time requirements. Scatter. However, in such a sequence control device, the number of controlled elements that can be controlled is generally limited by the number of bits per word of control data stored in the ROM. For example, if the storage capacity of the ROM is rpi) x 102ψ words, the output of the ROM/word has an l-bit configuration, so control data is supplied to only t controlled elements at each given timing. I can't. Therefore, in order to increase the number of controlled elements, it would be possible to install multiple ROMs in parallel, but this would result in excess storage capacity.
Storage space may not be used efficiently.

In the sequence control device of the present invention, in particular, the control data of the ROM is accessed in a time-division manner, and the storage space thereof is effectively utilized.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example of the configuration of a sequence control device for a copying machine to which the present invention is applied.
, a first high-voltage power supply 12, a second high-voltage power supply 13, a paper feed clutch/4 (, a resist clutch/3), and a plurality of controlled elements such as an optical system motor 16, a light source/7, and a fuser motor TG. The sequence control device has a read-only memory (hereinafter referred to as ROM)/9 and an address generator, and sequentially drives the above-mentioned controlled elements at predetermined timing to perform charging, exposure, development, and It controls the fixing process, paper feeding operation, etc. That is, the ROM/? stores control data for turning on/off the controlled elements at each timing, and has a storage capacity of, for example, !bin) x 102tI words. , the controlled element //-n is connected to each bit 0, to 08 of the t-bit output line.

The address generator consists of a rotary encoder 11 a transmission type photo sensor and a ψ bit counter n,
Specify the address of ROM/9. In this address generator I, a rotary encoder I is mechanically coupled coaxially with an electrostatic drum (not shown) of a copying machine,
Notches provided at predetermined intervals on the periphery of the
It is configured so that when it matches the transmission type 7 otosensor n, light from a light source placed opposite to it is transmitted at a constant period. Therefore, as the rotary encoder rotates, the transmissive photosensor generates a drum clock signal synchronized with the rotation of the electrostatic drum and supplies it to the counter n via the signal line 2g. The counter n is reset by a reset signal indicating the start of copying that is input from the control circuit (not shown) of the copying machine via a signal line, and then counts the drum clock signal supplied by the transmissive photosensor n. The counting result is output to terminal Q as an address signal. - Input terminal A of ROM/q via q-bit output signal line U from Q5. -Output to A3.

ROM/9c supplies control data for driving controlled elements // to /g to output bits 01 to 08 according to address fJ4 supplied by counter n. Therefore, if the operation of the controlled elements //-/g of the copying machine is determined as shown in the timing chart in Figure 2, the controlled elements //-/g are turned on in synchronization with the rise of the drum clock signal. / Off operation is coded, as shown in Figure 3.
The address of ROM/9 and the control data to be stored can be determined.

Next, the operation of the sequence control device shown in FIG. 1 will be explained with reference to the timing chart shown in FIG. 1 and the control data of the ROM shown in FIG. 3.

In the initial state of the sequence control device, ROM/9
Each output bit of 0. ~o8 are all 0'', and all controlled elements //~/l are stopped.Therefore, when the copy button (not shown) is operated to start the copying operation, the control circuit of the copying machine Since a reset signal is supplied from the signal line J to the signal line J, the counter n is reset in synchronization with the rising edge of the reset signal.
/9 address "o" is specified. As shown in FIG. 3, data for driving only the drum motor l/ is stored at address "0" of ROM/q, so the output bits of ROM/9 are 0. only output bits become /'', and the other output bits 02 to 08 become O''. In this way, when the drum motor // starts rotating, the transmissive photosensor n outputs a drum clock signal. The counter n increments according to this drum clock signal, and the ROM/
The addresses of ROM/9 are sequentially designated, and a series of sequences shown in the timing chart of FIG. 2 are executed using the output data of ROM/9. Then, when the address of the ROM / becomes l ts n, the drum motor / stops and the drum clock signal disappears, completing the copying.

As described above, according to this embodiment, the control data at the address specified by the address generator is read out from the ROM in synchronization with the clock signal to drive the controlled element, so it only has real-time performance. In addition, the coding of the timing chart and the control data in the ROM match perfectly by associating time and address, so coding is simple, there are fewer errors, and corrections and changes are easy. A highly reliable sequence control device is obtained. Therefore, the sequence control Mft of this embodiment also includes (1) specification determination, (2) timing chart creation,
This can be achieved using much simpler means than conventional methods, such as (5) coding and (4) examination of actual equipment. Furthermore, in this example,
By simply rewriting the control data in the ROM, the present invention can be applied not only to sequence control devices for copying machines but also to various sequence control devices for other uses.

FIG. 1 shows another example of the structure of the sequence control device for a copying machine according to the present invention. Note that the same parts as in FIG. 1 are denoted by the same reference numerals, and detailed explanation thereof will be omitted. This sequence control device is composed of an address generator 3, a ROM 32, and t latch circuits 33~%, and controls the exposure, development, and fixing processes of the copying machine, as well as mechanisms such as paper feeding.

Address generator 3 is ROM,? Lower address A of λ
.

~A3 and address signals specifying upper addresses A4 to A6 are generated.

In this address generator 3/, a rotary encoder, a transmission type photosensor n, and a first
Counter n is the lower address A of ROM3x. A t-bit address signal specifying .about.A is generated. Further, the address generator 3/ outputs the upper addresses A4 to A4 of the ROM3.
In order to generate a 3-bit address signal specifying A6, an oscillator G/ and a first counter N are provided. The oscillator 'l/ is the drum clock signal! more than twice (in this example r
oscillates a system clock signal having a frequency of 33% to 30%, and supplies it to the clock terminals OK of the first counter nλ and the latch circuits 33-%. The first counter n2 is a 3-bit counter that counts the system clock signal and
Upper addresses A4 to A6 of OM 32 and latch circuit 3
It outputs an address signal specifying addresses An of 3 to p.

The latch circuits 33 to 33 are addressable latches,
The address is specified by the address signal of the first counter n,
Further, in synchronization with the system clock signal of the oscillator G/, R
Control output data 01 to 08 of the OM 32 are latched via input terminals, respectively. In addition, the latch circuit 33~ψ
have t-bit output terminals QA to Q, respectively. Therefore, the total number of controlled elements controlled by the latch circuits 33 to 33 is rxr=+<< pieces, and the control signals O1A to Oi (however, 3 .-/, 2, 3...
9. r) can be supplied to the controlled element.

ROM 3r has address A as shown in the figure. - Since A6 is 7 bits and control output data 01 to 08 are t bits, it has a storage capacity of 1 bit x/2t words, but the control data is read out by time-sharing access as described below. As a result, it functions as a 6II bit x/≦word ROM. As shown in FIG. 5, the address map of this ROM 32 is composed of control data 0, . ~08 and every 16 words /
It consists of t blocks A to H, and formally has a structure of t bits×l user words. However, in the illustrated address map, addresses are displayed in /quaternary notation.

Next, the operation of the sequence control device shown in FIG. 2 will be explained with reference to the address map shown in FIG.

In the sequence control device, in the initial state, the outputs O5 to 08 of the ROM3λ are all O'', and the latch circuit 3
Since "O" is latched in 3 to 4, all 6 controlled elements are stopped.When the copy start button (not shown) is pressed, a signal is sent from the control circuit of the copy machine. The first counter n receives the reset signal supplied via the line B, and sends to its output terminal Q.-Q3 an address signal ``(O) specifying the lower address A.-A3 of the ROM 32,
6". At this time, the oscillator dal outputs the first counter n
In order to supply a system clock signal to the first counter n2, the first counter n2 outputs an address signal specifying the upper addresses A4 to A6 of the ROM 32.

As mentioned above, the system clock signal is set to have a frequency j times that of the drum clock signal, so as the electrostatic drum (as shown) rotates, the first drum clock signal becomes the signal. The first counter n via line 2
The upper address A4 of lROM 32 is input to
The address signal that specifies ~A6 is @ (1) 1. IT
It changes from ``(7)1.''. That is, on the address map, as is clear from FIG.
, B, 0. . . , ■ are specified sequentially. Meanwhile, R.O.
Lower address A of M32. The address signal specifying ~A3 remains ``(O), 6', so address A.-
The address signal specifying A6 is “((”)16”
T ” (”) 44 ” +” (ko 0), 6” +...
+” (70), 6”, and the ROM 32 stores /word t bit control data 0 according to each address.
Outputs °~08. At the same time, the second counter tag 2
supply address signals to the address input terminals An of the latch circuits 33 to %, respectively, and the oscillator Da/ supplies the address signals to the address input terminals An of the latch circuits 33 to
Since the system clock signal is supplied to the clock input terminal OK of the rabbit, the latch circuits 33 to p receive the control output data 01 to 08 of the ROM 32 via the input terminals, respectively.
can be interrupted in a time-sharing manner.

Next, the electrostatic drum starts rotating, and the transmission type photosensor n detects the light that has passed through the notch of the rotary encoder, generates a drum clock signal, and sends the drum clock signal through the signal line 2. When the first counter n receives the signal, the first counter n increments the count value by +゛/”. Therefore, the first counter n
The address signal generated at the output terminal Qo "" Q4 is "
(1), 6', lower address A of ROM JJ.

-Specify A5. At this time, the first counter n2 counts the system clock signal and sequentially outputs "(7), 6" from l (o> 16n) until the first counter n receives the next drum clock signal, Specify upper addresses A4 to A6.

Therefore, during this period, ROM,? 2 address A. −
For A6, "<0/), 6 ' * " (//)
16”.

'(71)16'' is specified, and the ROM 32 sequentially outputs the control data of the specified address.Synchronizing with this, addressing and latch control of the latch circuits 33 to ψ are performed as described above. Therefore, the control output data O4 to 08 of the ROM 32 is distributed to each latch circuit 33 to °p in a time-division manner according to the system clock signal.
At timing 6, the ROM 32 reads all control data, and the latch circuits 33 to 3 can read the control output data of the ROM J2 at each timing in synchronization with the system clock signal. Next, the latch circuits 33 to 33p receive their control output data 01,5 +
(However, ' = / l, 2+...,, r,,
+=A, B+..., H), respectively, to the controlled elements.

Therefore, this sequence control device can control B≠ controlled elements based on the ROM 320 control data at a timing of /4.

Here, although the ROM 32 has a storage capacity of f bits x/2 words, it functions as a ROM of 6t/- bits x/l words 5 by performing the above-mentioned time division allocation. can do. Therefore, according to this embodiment, the number of controlled elements can be increased without being limited to the number of bits per word of the ROM.
OM storage space can be used efficiently. Furthermore, since the timing chart and the control data in the ROM correspond, the same effects as in the previous embodiment shown in FIG. 1 can be obtained.

Figure 1 shows still another example of the structure of the sequence control device for a copying machine according to the present invention. Components common to those in the previous embodiment shown in FIG.

This sequence control device has an address generator J/1 enable signal generator SLLROM 3x and t latch circuits 33~%, and is suitable for relatively long sequence control that continuously generates the same control data. .

The signal generator J/ generates an enable signal that allows the third counter j2 and the magnitude comparator j3 to fL and the first counter n of the address generator 3/ to count. The third counter j2
resets its contents in response to the load signal supplied via the signal line sti, then counts the number of pulses of the drum clock signal supplied via the signal line jj, and calculates the unsigned number that is the counting result. The binary value B is supplied from the output terminal Qn to the magnitude comparator S3 via the signal line j7.

The magnitude comparator 3 outputs a signal line from the supplied unsigned λ base value B and the width of each output terminal of the launch circuits 33 to ψ! Compare the run length data supplied via B, that is, the unsigned binary value A indicating the time for consecutively generating the same control data, and only when the values of both A and B are equal, signal line jl is connected. through the first counter n
An enable signal is provided to allow the counting. 1st
The counter n increments the drum clock signal at the timing of receiving the enable signal, and stops incrementing at other times. At the same time, the enable signal is also supplied to the clear terminal OL of the third counter S2 via the branch signal line j9 indicated by a broken line to clear the count contents.

In advance, the A-G area of ROM 32 (see Figure 5)
The output control lines O1A to 01G of the latch circuit 33 to
(However, the controlled element drive data (control data) corresponding to the output value of '''''/lλ, 3...t) is stored, and the remaining H area (see Figure 3) stores each address. Run-length data corresponding to the time during which the control data continues is stored as an unsigned co-decimal number consisting of /sets t bits. In addition to the above-mentioned ROM 32, a second ROM connected to the signal line may be separately provided, and the run length data may be stored in the J-th ROM.

Next, the operation of the sequence control device shown in FIG. 1 will be explained with reference to FIG. 5 as well.

From the time when the first counter n sends out the first address signal in response to the reception of the reset signal, only the output of the control line 02A of the latch circuit 3 is set to high level H during the period of vS clock pulse in terms of the number of drum clocks. Assuming that the output of other control lines is kept at low level LK: In that case, the address of ROM 3λ is set in advance @ (
oo ), 6P+ has unary data (ooooooto
>2wo, address? +(7o)16” contains lambda-adic data (
0010/10/ ), = (pt),. Also, the address "(10)"! ” (-20), 6”
l”<30)16”.

6 ′(lIO)16”+ ” (jO)16” O and ゛(”)16” are all binary data (00000000)
Insert 2.

Therefore, when the first counter n sends out the first address signal "(O), 6" indicating the lower address and the second counter II2 sends out the upper address signal, the ROM 3
2 (7) 7 dresses" (nil□), 6'," (
/(7), 6”.

″(20)″ n (30), 6″, −”
(")L6" is sequentially selected six times, and the above-mentioned unary data written to that address is supplied to the input terminals of the latch circuit 33--phrase.

At the same time, the address signal of the first counter n is supplied to the address input terminal An of the launch circuits 33 to 4to,
The system clock signal of the oscillator is sent to the latch circuit 33~
% is supplied to the clock input terminal OK, so the latch circuits 33 to 4to are supplied with the ROM
32 control output data 01 to 06 are read in time division in synchronization with the address signal and the system clock signal.

That is, when addresses "(oo), 6" of ROM n are selected, the co-decimal data (O
OOOOOlo) 2 is a latch circuit, ? ,? - Supplied to the rabbit input terminal. Since the control output data at this time is only 02 is /'' and the others are O'' (see Figure 5), as a result of being read in time division, the control output data 0. 02 within A~08A
Only the output of A is high level H, the others are low level L
becomes. Next, address ゛(10)16 of ROM3x
"~゛(60), 6" are sequentially selected, and the data is read into each latch circuit 33-p in time division, or the λ-adic data (oooooooooo) which is all zero is stored in those addresses.
)2 is written, all the corresponding control lines are at low level L. As a result, 56 output control lines 0
Among the signals 1A to 01G, only the output of the control line 02A becomes high level H.

Next, when the address "(70), 6" of ROM 3x is selected, the λ-adic data (0
010/10/)2 is read into the latch circuits 33-4to and sent out via the signal line j6. At that time, t output control lines O1H to 08H are output as one data to the signal line jB, and the co-digital data (0010/10/)2 corresponding to the clock pulse is input to the magnitude comparator j3. Supplied to terminal A. On the other hand, the third counter j2 reads its contents (oooooooo) by the load signal that is generated almost simultaneously with the generation of the reset signal.
2, the drum clock signal supplied from the rotary encoder is counted, and the unsigned co-decimal number B, which is the counting result, is supplied to the input terminal B of the magnitude comparator j3. Comparator 53 is input terminal A
The co-decimal data supplied to input terminal B is compared with the co-decimal data supplied to input terminal B, and the enable signal is set to high level H only when the values of both data match. Therefore, the third
Counter j3 counts the drum clock signal by ttS clock pulses, and the count value B is equal to (OO10
The first counter n does not increment until it becomes equal to /10/)2, and only the output control line 02A maintains a high level H''C control output state.

Next, run length data A (0010/10/)2
When and drum clock count value B become equal, the enable signal becomes high level H, so the first counter n is enabled to count in response to reception of the enable signal, and advances by 10''/'' in response to the drum clock signal. . At the same time, the contents of the third counter S,2 are incremented by the enable signal 6/, and the next control state is entered. Here, if /byte r bits, the ROM required for the previous control is
3.2 storage area! However, if sequence control similar to this is executed using the method of the previous embodiment shown in FIG. 1, 5 x 1 bytes = 360 bytes will be required. Furthermore, if the run length data of (//////// )2 is stored in advance at the address "(71)16" of the ROM 32, the output control state in the next control stage is set to the drum clock, and ! ! ;Can be made continuous for pulses. Similarly, output control line OiA~01c)
The control data output from the ROM 32 address "(
72) 16Z" (73n, 6"..." (7F
) 16'' can be continuously output according to the run length data stored in advance.

In this way, in the non-embodiment, when the same control data continues, the run length time indicating the continuous time is encoded and R
Since the run length data is stored in advance in the OM and sequence control is performed based on the stored run length data, the ROM
storage capacity can be significantly reduced. Therefore,
This embodiment is particularly suitable for relatively long sequence control in which the same control data continues to be output. Furthermore, in this embodiment, since the third counter 3.2 is cleared in synchronization with the enable signal, the counter 3.2 counts the number of drum clocks from one point to another in the control output. Therefore, even if the counter j2 has a bit configuration, there is an advantage that sequence control over two days is possible with the number of drum clocks.

Still, in FIG. 4, the address line O of the first counter n2 is connected to the ROM,? , 2 lower address terminal A. ~Connect to A2, address string 6ROM of first counter n,
? When connected to the upper address terminals A3 to A6 of 2, the 7th
As shown in the address map in the figure, the ROM3j no address arrangement is extremely rational. That is, in this case, seven sets of bytes constitute a run-length instruction, which facilitates program design. In other words, for the first 7 bytes of each set of bytes, it is sufficient to write the output status of the output signal line in bit correspondence, and in the lth byte, write the length for which the status continues as an unsigned double code. be.

Of course, it is not necessary to allocate the run-length code to the same memory space as the ROM 32, and the second ROM (not shown)
You may also assign it using . In this way, when inserting a run-length code into the second ROM, connect the address line of the second ROM to the above-mentioned address line n, and connect the data line to the magnitude comparator j.
The output data can be directly applied to the comparator j3 by connecting to the A input terminal of the comparator j3.

Note that the first counter knife in each of the embodiments shown in FIGS. 7 to 6 may be equipped with a preset function. For example, it is preferable to use a microcomputer (not shown) as this preset.
The control operation can be started from the middle of the timing chart as shown in the figure. Furthermore, in that case, the microcomputer is completely freed from normal sequence control, so it can concentrate on more advanced control. In this way, in each of the above-mentioned embodiments, a microcomputer is assumed to be used for exceptional sequence control such as condition judgment, but furthermore, the application of the present invention is simply slow sequence control such as sequence control of a copying machine. In addition, it can also be applied to ultra-high-speed sequence control such as (7) Ic LSI f-star, which will be described later. In this case, a bit slice type microprocessor can be used as the microcomputer.

FIG. 5 shows an example of the configuration of an LSI tester to which the present invention is applied. Components common to those in FIG. 9 are designated by the same reference numerals 1 through 1, and detailed explanation thereof will be omitted. Here, 7/ is input condition data (test input data) from address pull latch circuit 33~%
7. LSI under test (Large scale integrated circuit) to which is supplied;
2 is an input register that checks the response result of the LSI under test 7/, and 73 is a logical operation unit (ALU) that controls the output register 7S via the data bus 7tI based on the output data of the input register 7λ. . LSI 7/ corresponds to the controlled element of the previous embodiment, and ALU 7j consists of, for example, a bit slice type microprocessor. The output register 7j is a lower address A of the ROM 32 from which input condition setting data of the LSI 7/ is read. -A, performs address control to instruct. In this way, since the ALU 73 is freed from normal sequence control, operations other than relative addresses can be executed with the /byte instruction, which enables high-speed data control. A high-speed LSI tester can be configured.

A program memory 76 is composed of a read-only memory, and includes a register control bit area R1, a memory control bit area, a data bit area, and a command bit area C. Area R is an area for manually accessing the register 72, and area M is an area for random access memory (RAM).
) 77, a program counter (PO) 77, an output register 73, etc., and an area for supplying data (expected output data) to the ALU 7J.

Area C is an area for controlling the operation mode of the ALU 73, and stores bits instructing which function of the ALU 73 is to be used. Since the program memory 76 consists of /instructions and /bytes, the program memory 76 is normally incremented once every l instruction is executed.

If the command bit (0) is a jump command, directly fetch the value of the memory control bit (M) from the absolute address, add or subtract the current value of PO71 from the relative address, and fetch again. .

The RAM 77 is chip-selected by the register control bit of the program memory 7B, and the cell is selected by the memory control bit OL of the program memory 76. ), the input data sent on the data bus is read or the stored data is output to the data bus 7II.The PC 71 controls the address of the program memory 7B. 7B This is an index register used for twin text instructions.Here, the case where the RAM 77 is accessed by a signal from the index register 79 is referred to as an index address, and the case where the RAM 77 is accessed by a signal from the memory control bit area M of the program memory 76. When accessing, use a direct address.

A register 10 is used as a scratch pad memory for various operations of the ALU 73, and data necessary for logical operations is written to this register 10 and processed.

g/ is an input/output register that receives and transfers data to and from an external device (not shown), and, for example, specifies addresses of input/output devices and sends and receives data. External devices include video keyboards and line printers, which are used to input test programs and output test results.

Next, the operation of the LSI tester shown in FIG. 1 will be explained.

First, at the start of the test, an address signal is sent from the output terminal Q of Carantuff 2, which counts the output of the oscillator (080) Il/, and this signal causes the ROM, ? 2 upper addresses A4 to A6 are specified, and the output register 7j
The lower address A of ROM J,2 is determined by the address signal sent from ROM J.2. -A5 is specified. designated RO
The data at addresses A0 to A6 of M3λ are sequentially sent from the output terminals 01 to 08 to the corresponding addresses of the latch circuits 33 to 33. As a result, output control lines 01□ to 01Y (however,
1-7~g) through human test data, i.e. RO
The test pattern data corresponding to the input conditions written in M32 is input to the input terminal check of the LSI under test '7/.

~ 63, and the response results are sent out from output terminals O6~01o as detection outputs. Here, for example, when this device is used as a calculator LSI checker by combining the calculator LSI with the LSI under test 7/, the above-mentioned input end checker is used. . . . 25 correspond to the input terminals of the numeric keypad of the calculator, and the output terminals 06 to 010 correspond to the liquid crystal drive output terminals.

The detection output from the LSI under test 7/ is stored in the program memory 7.
A register control bit R accesses the AL
Supplied to U 73. The ALU 73 measures the output values for various key manual states based on the supplied detection output, and calculates the accuracy in the case of a non-defective product, which has been calculated in advance based on the data supplied from the program memory 7t (CD). It is determined whether the LSI 71 under test is a good product or a defective product by comparing it with the output value and checking whether the two match. The determination result is sent to an external device via an input/output register and displayed or printed out. When moving on to the next test, AL
An instruction signal is output from U 73 to output register 7j, and based on this, a new address instruction is issued from output register 7j to ROMn K, which causes the LS under test to
I7/ will be given new manpower requirements. At this time, the latch circuits 33-% only latch the contents written in the ROM 3 based on the output from the output register, so the processing speed is extremely high. For example, latch circuit 3
3 to % are respectively assigned to the output ports of the microcomputer, and the output values are set by software.

It is possible to operate at least 10 times faster than in the conventional case.

In this way, in this embodiment, if a timing chart is given, sequence control can be performed by simply writing it directly into the ROM K, compared to a conventional sequence control device that requires complicated software using timer control. This not only greatly reduces the development effort, but also reduces the development effort to zero when combined with a bit slice processor.
The effect of realizing high-speed sequence control of testers, etc. can be obtained.

As described above, according to the present invention, it is possible to provide a sequence control device that is a flexible and versatile system and also satisfies real-time performance by time-division access of the ROM.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the basic configuration of the sequence control device of the present invention, Fig. 1 is a timing chart showing an example of the output waveform of the control signal shown in Fig. 1, and Fig. 3 realizes the control output shown in Fig. 2. FIG. 11 is a block diagram showing another configuration example of the sequence control device of the present invention, and FIG. 5 is an example of the address map of the ROM shown in FIG. An explanatory diagram showing,
FIG. 6 is a block diagram showing still another configuration example of the sequence control device of the present invention, FIG. 7 is an explanatory diagram showing an example of the address map of the ROM in FIG. 6, and FIG. 1 is an L to which the present invention is applied.
FIG. 2 is a block diagram showing a configuration example of an SI tester. l/...Drum motor, /2...7th high voltage power supply, 13...2nd high voltage power supply /+7...Paper feed clutch, /3...Register clutch, /6...Optical system Motor, 17...Light source, /l...Fuser motor, 19...Read only memory (ROM),
〃...Address generator, I...Rotary encoder, n...Transmissive photo sensor, n...Counter (first counter), 2G...Signal line, B...Signal line, To...
・Output signal line, 3/...address generator, 3no...read only memory (ROM), 33~4to
...Addressable latch circuit, (Z/...oscillator (
OSO), gλ...first counter, jl...
Enable signal generator, j2...Third counter, jl...Magnitude comparator, evaluation~j9...
・Signal line, function...address line, 7/...LSI under test (controlled element), 7λ...input register, 73...logic operation unit) (ALU), 7...
・Data bus, 7j...Output register, 7g...Program memory, 77...Random access memory (RAM), 7g
...Program counter (PC), 79...Index register, 10...Register, Su/...I/O register. Patent applicant Canon Co., Ltd. Figure 5

Claims (1)

[Claims] A read-only memory that stores control data for a plurality of controlled elements, and time-sharing access to the control data of the read-only memory by generating address signals that specify the upper and lower addresses of the read-only memory at different cycles. 1. A sequence control device comprising: an address generator for latching control data read from the read-only memory at a predetermined time; and a latch circuit for latching control data read from the read-only memory at a predetermined time.