JPS6160142A - Dynamic burn-in method for microcomputer with prescaler - Google Patents

Abstract

PURPOSE:To apply a test pattern in common to many ICs and to attain a burn-in action by supplying clocks until the state of a prescaler of a microcomputer can fetch an instruction. CONSTITUTION:A rest switch 10 turned on to clear a counter 3 and to reset monostable multivibrator 2. Thus the CLK of a clock terminal 9 is applied to the Extal of a CUT1 through NAND gates 5 and 6. When an F/F of a prescaler of the DUT1 can fetch an instruction, a terminal E(IRU) of the DUT changes to H from L. Then an input is supplied to the input B of the multivibrator 2. The output Q of the multivibrator 2 is changed to H from L, and NAND gates 4 and 5 are kept closed. Thus the supply of clocks is stopped to the DUT, and the F/F of the prescaler is put under a waiting mode in an instruction fetch enable state.

Description

[Detailed Description of the Invention] [Industrial Application Field] In particular, dynamic burn-in (BurnIn) involves exposing a single-chip microcomputer to a high-temperature environment while actually operating it to detect early defective products. Regarding.

Figure 6 shows the failure rate of a single-chip microcomputer. In the figure, (I) is an early type failure area with a high failure rate, (II) is an area with few failures, and (■) is a degraded mode failure area.

Before shipping a one-chip microcomputer, it is necessary to eliminate the factors that cause the initial type of failure (1).

[Conventional technology]

Conventionally, the following methods have been used to eliminate this initial type defect.

■ Static Burn-in (Static B
I) Apply bias to the microcomputer under high temperature and leave it for a specified period of time,
Excludes defective products.

■ Clocked Burn In (C1ocked B
I) In addition to biasing the microcomputer at high temperatures, we also put in a clock and operate it for a specified period of time to remove defective products.

■ Dynamic Burn-in (Dynamic B
I) Apply a test pattern to the microcomputer, wait for a predetermined period of time while operating the microcomputer, and remove defective products.

In the old days, only static BI was performed, for example, DC
Only the power supply voltage was applied, and the products were placed in a high-temperature room at about 125° C. for a predetermined period of time to remove defective products. However, since the microcomputer is not operating, it is not possible to sufficiently eliminate early failures. In recent years, it has become common practice to perform Clocked BI (Clocked BI) and perform burn-in after supplying CLK to the microcontroller and not operating it, but only a portion of a single-chip microcontroller can be operated by clock application alone. It is.

Therefore, in order to perform a more rigorous burn-in and eliminate those that cause early failures, we decided to
is required to do so.

[Problem that the invention seeks to solve]

However, today, single-chip microcontrollers have a prescaler (e.g.
For example, it has two flip-flops), and the CL
K is divided into a predetermined frequency, and at that point a pulse is generated to switch the instruction. However, in order to use a 1-chip microcontroller alone, the prescaler F
It does not have a reset circuit because there is no need to reset /F. Therefore, in the above dynamic BI,
If you try to operate hundreds of 1-chip microcontrollers by connecting them in a parallel manner, each instruction will be switched at a different position, making it impossible to drive them in a parallel manner. Therefore, conventionally, when attempting to dynamically burn in a large number of one-chip microcomputers at the same time, one driver must be connected to each microcomputer, resulting in a problem that the burn-in cost increases significantly.

[Means for solving problems]

In the present invention, the F/F of the prescaler is kept in the same state for all samples, and therefore the clock supply is stopped when the F/F of each one-chip microcontroller reaches a predetermined state, a state in which instructions can be switched. , The process starts when all samples are in the same state. In this way, one driver can commonly supply instructions to operate each sample, and therefore the cost of dynamic BI can be significantly reduced.

〔Example〕

FIG. 1 shows a circuit according to an embodiment of the present invention. The prescaler synchronization circuit for matching the F/F of the prescaler of one chip microcontroller has two circuits, one chip microcontroller test device (DUT) and one chip microcontroller test device (DUT). It consists of a UT enable standby circuit 11, which is required for each DUT 1, and a lock supply/synchronization start circuit 12, which is common to each DUT 1. DUT enable standby circuit 11 consists of mono 4 multi 2 and Nantes gate 4
, 5.6. On the other hand, the clock supply/synchronization start circuit 12 is connected to one terminal of the counter 3 (here, 4 pits) and the side gate 4.5, and the most significant bit QD of the counter 3 is connected to the other terminal of the gate 4. The inverted output Q of the monomulti 2 is connected to the other terminal of the NAND gate 5. The outputs of the Nant gates 4 and 5 are connected to one and the other terminal of the Nant gate 6, the output of the Nant gate 6 is connected to the Eztal terminal of DUT 1, and the E (IRU) terminal of the DUT is connected to the mono multi 20
Connected to input B. A reset terminal R of the DUT is connected to a reset switch 10.

Clock input terminal CLK of counter 3 is clock terminal 9
The other terminal of the Nant gate 8 is connected to the terminal of the topmost pin (QD) of the counter 3 via an inverter 7. A reset switch 10 is connected to the CL terminal for clearing the contents of the counter 3.

The operation of the circuit is as follows: First, reset switch 10 is turned on to clear counter 3, and when monomulti 2 is reset, QD of counter 3 becomes zero (L'').

The inverted output Q of the monomulti is ``H''. Therefore, the input of the Nant gate 5 is ``H'', and the input of the Nant gate 4 is ``L''.
”, Nantes Gate 5 opens and Nantes Gate 4 opens.
closes. Therefore, the CLK of the clock terminal 9 passes through the Nant gates 5 and 6, and when the state of the DUT 1/F becomes available for instruction switching, the terminal E (IRU) of the DUT changes from "L" to "H".
Change to I+ and input to mono multi input B. Mono multi 2 captures the startup and output Q changes from L” to “H”
Therefore, Q changes from "H" to "L". Therefore, the input of the Nante gate 5 changes to "L" and closes. In this state, both the Nante gates 4 and 5 remain closed, and the supply of the clock CLK to the DUT is stopped. Therefore, the prescaler F/F of the DUT 1 is Waits in a state where commands can be switched.

On the other hand, counter 3 indicates that the top pit QD is l I, I"
Therefore, since the input of the Nant gate 8 is 'H°' and the gate is open, the CLK of the clock terminal 9 is supplied to the counter 3, and the count advances to 0, and the counter reaches a full count (in this case, it is a 4-bit counter). from 1
111) Then, QD changes from "L" to ")I", so the input of Nantes gate 8 becomes 'L' and the gate closes, so the clock supply stops and counter 3
is in full count ＼holding 8). Therefore, QD is always 'H', Nantes Gate 4
Since the input becomes "H", the Nante gate 4 opens. That is, all the DUTs in the standby state are supplied with the clock CLK and started at the same time. In addition, in the above, the CR time constant of Mimono Multi 2 must be set to be larger than that of the E signal input to the B terminal.

FIG. 2 shows a time chart when the prescaler of the above-mentioned embodiment divides the frequency by 4, and the F/F of DUT 1 shown in FIG. 1 is set to enable instruction switching in the second cycle of clock CLK. As shown below, the output of the E (IRU) terminal of DUTI changes from l″L” to “H” in the second cycle of clock CLK, and CLK (Extal)
The clock stops and the device enters standby mode.

Similarly, other DUTs 2, 3, 4, etc. also enter the standby state, for example, at the third, fourth, and first cycles of the illustrated clock. When the prescaler is divided by 4, the clock CLK for all DUTs
Standby state (all E signals are “H”) within 8 cycles of
It is clear that it is guaranteed that and,
When the most significant bit QD of the counter becomes 1'' (“H” level), the clock CLK starts being supplied to each DUT, and each DUT can start in a synchronized state. In this way, the prescaler Once synchronized, all that is left is to apply test patterns from the E-ROM to other terminals at the same time, making dynamic BI possible.

Figures 3 and 4 show the overall configuration for implementing this dynamic BI.
~1) are individually provided with the DUT enable standby circuits 11 shown in FIG.
A synchronous start circuit 12 is connected. -Yuna DUT (
The other terminals 1 to 1) are commonly connected to a line 32 connected to a driver 31 of the test pattern generation container. FIG. 4 shows a dynamic BI device using the prescaler synchronization circuit shown in FIG. Clock supply/synchronization start circuit 12, test pattern generator 30. Driver 31 etc. are arranged,
High temperature tank 42 (for example, Ta=1
25°C). Dynamic BI is performed for 48 to 96 hours, and then the DUT is removed from the high temperature bath and tested by another method to remove the defective 1-chip microcomputer.

Above, the case where the prescaler of the DUT divides the frequency by 4 has been shown as an example, but it is not limited to this, and can be applied to, for example, divide by 6, divide by 12, etc. In that case, as shown in FIG. It is obvious that the number of bits in counter 3 should be increased.

Next, an embodiment of the test pattern generator 30 will be described with reference to FIG. Pattern memory (1) 51 is, for example, 1
It is a 920 Kbit EP ROM, and patterns for 40 pins are written therein. This pattern memory (1)
In order to generate a pattern from , a pattern counter 54 for incrementing the memory address and a controller (microprocessor) 53 for controlling this are provided as a mechanism for generating an address. Pattern memory (1)
is the function pattern L applied to the DUT, but F
RAM of T Function Pattern
.

Pattern excluding ROM (same as tester pattern)
). In the case of the test pattern between RAM and R6, there are many repetitions, and the pattern length becomes too long in the case of a continuous pattern. Therefore, for patterns that are difficult to store in memory, such as test patterns between the RAM and R6, the controller 53 is configured to function as an algorithmic pattern generator. Therefore, a pattern (2) 52 is provided, and a program (RAM, ROM (7)) is provided to generate instructions to be applied to the DUT.
(pattern and pattern generator control program)
Write it down. The capacity of pattern memory (2) is IKby
te is sufficient. The controller 53 reads the program from the pattern memory (2) and uses it to generate instructions. In this case, since an 8-bit microcomputer is used as the DUT, the instructions are for the 8 bins shown.

In this way, under the control of the controller 53, the line 6
3 and 62 have patterns for 4o pins and 8 pins, respectively.
While instructions for the bins are provided, controller 53 sends a control signal to multiplexer 55 via line 61 to switch which signal is sent to the DUT. In order to provide versatility, it is preferable to perform this switching for all 40 pins, but in this example, it is sufficient to perform this switching for only 8 pins. For the remaining pins, a pattern of line 63 may be given. When switching the multiplexer for 40 pins, a fixed 0.1 pattern may be given to the remaining pins.

Next, a case where the counter 56 is used will be explained.

The above-mentioned test pattern is generally generated for each well-organized cycle such as an instruction cycle. However, since the required timing differs depending on the pin of the DUT, it may be better to include a waveform that changes in a specific state of the instruction cycle depending on the pin. In particular, when hundreds of DUTs are connected in parallel and a test pattern is applied, the waveform provided becomes dull, so if the test pattern waveform is applied to the pins at too strict a timing, it may not work. Therefore, the counter 56 divides the clock CLK to generate a timing signal Tl-Tm for each state of the instruction cycle.
A DFF (S1 to 40) is provided corresponding to each pin of the UT, and a desired timing among T1-Tm is input to the control terminal Tn. In this way, it becomes possible to set the timing of applying the test pattern depending on the pin, and it is possible to apply the test pattern waveform to each pin at a timing with some margin.

The control of the pattern counter 54 will be outlined.

When the controller 53 is generating an instruction using the pattern memory (2) 52, the controller 53 applies an inhibit signal to the AND gate 57 and closes the AND gate 57. Therefore, the pattern counter 54
Since the clock CLK is no longer input to the counter, the counter stops and the pattern memory (1) becomes inactive.

In addition, the controller 53 controls the R of the pattern counter 54.
A reset signal is sent to 8T, and when the pattern counter 54 finishes counting, the CARRY terminal sends a completion signal to the controller.

Hikoo, in the circuit shown in Figure 5, the pattern memory (1),
The pattern memory (2) is typically a ROM (P R
OM.

It is composed of EP RCIM, E ROM), and has a structure that can be replaced as necessary. . Further, the pattern memory (1) and the pattern memory (2), which is a storage device of the controller, may have an integral structure.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to synchronize the operating states of each type of IC that has an internal clock source and runs on its own, such as a one-chip microcomputer that operates a prescaler. .

Therefore, it has become possible to dynamically burn-in a large number of ICs by applying a common test pattern to them, which was previously impossible.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a prescaler synchronization circuit according to an embodiment of the present invention, Fig. M2 is a time chart of the prescaler synchronization circuit, Fig. 3 is an overall circuit diagram of an embodiment of the present invention, and Fig. 4 is a circuit diagram of the prescaler synchronization circuit according to an embodiment of the present invention. Layout diagram of one embodiment, (Main symbols) 1...DUT, 2...One-shot multi, 3...
・Counter, 4.5.6.8... Nantes Gate, 7.
... Inverter, 9... Clock terminal, 1o... Reset switch, 11... DUT enable standby circuit, 12... Clock supply ° synchronous start circuit, 30
...Test pattern generator, 31...Driver, 5
1... Pattern memory (1), 52... Pattern memory (2), 53... Controller, 54... Pattern counter, 55... Multiplexer, 56...
Counter, 57...and gate.

Claims (2)

[Claims] (1) In the dynamic burn-in method, in which a test pattern is applied to multiple microcomputers equipped with a prescaler, they are operated in a high-temperature atmosphere, and initial defective products are removed. a circuit for supplying a clock from the clock supply terminal until the state of a prescaler of the microcomputer becomes such that an instruction can be switched, and stopping the clock supply according to an enable signal of the microcomputer; a circuit that starts supplying a clock from the clock supply terminal to the plurality of microcomputers in a state where a prescaler of the microcomputer can switch instructions; and a circuit that commonly supplies a test pattern to other terminals of the plurality of microcomputers. A dynamic microcomputer with a prescaler is characterized in that it synchronizes the states of multiple microcomputers and performs burn-in.
Burn-in method. (2) The circuit that commonly provides the test pattern includes a storage device that stores a function pattern to be applied to the microcomputer, and a controller that reads a necessary pattern from the storage device and performs control to apply it. A microcomputer with a prescaler according to claim 1, comprising an algorithmic pattern generator and a circuit that selectively outputs the pattern read from the storage device and the algorithmic pattern. Dynamic burn-in method.