JP3240630B2 - IC tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester, and more particularly to control of a pattern generator.

[0002]

2. Description of the Related Art A conventional IC tester tests the electrical characteristics of a DUT by applying a power supply voltage or a signal to an IC under test (hereinafter referred to as a DUT) and comparing an output signal from the DUT with an expected value. Things. Especially IC functions and A
When testing the C characteristic, the operation of the IC is tested using data called a test pattern obtained by performing a logical simulation on a computer.

[0003] As ICs become more highly integrated and more sophisticated, the test pattern capacity used for testing becomes longer and may be larger than the capacity of an execution test pattern memory (hereinafter referred to as a test pattern memory) inside an IC tester. In this case, one test pattern capacity must be equal to or smaller than the pattern memory capacity, and is divided into a plurality of test patterns smaller than the test pattern memory capacity that are larger than the test pattern memory capacity and used for the test.

When a test pattern is created, a single IC has a plurality of test patterns in order to create each functional block inside the IC, so that a test can be performed using the plurality of test patterns. is there. In particular, the tendency is remarkable in the microprocessor IC.

Referring to FIG. 3, a description will be given of a case in which an IC is tested using such a plurality of test patterns. FIG.
(A) is a block diagram of a pattern generation mechanism of an example of a conventional IC tester. FIG. 3B shows an example of a test program using three test patterns A, B, and C.
(C) shows the processing operation inside the IC tester in the section P in the test program of FIG. 3 (b) with time.

In FIG. 3A, 1a is a control unit, 2a is an address control unit, 3a is an address generation unit, 7 is a pattern memory unit, 13 is a timing generation unit, 9 is a format unit,
0 is a pin electronics section connected to the DUT 12. The "POWER ON" and "POWER OFF" command statements in the test program shown in FIG. 3B apply the power supply voltage from the IC tester 20b to the DUT 12, respectively.
"TEST" A "" and "TEST"
“B” and “TEST“ C ”” mean that testing is performed using test patterns A, B, and C, respectively.

In this test program, the IC tester 2
The control unit 1a inside 0b applies a predetermined power supply voltage to the DUT in response to a "POWER ON" command. Next, the control unit 1a sets a voltage level of a driver and a comparator inside the pin electronics unit 10 (hereinafter, abbreviated as a DC level) by a command of “TEST“ A ””, and a signal path between the pin electronics unit 10 and the DUT 12. Close the relay and make an electrical connection. Further, the control unit 1a sends the head address data of the test pattern A in the pattern memory 7 to the address generation unit 3a to the address control unit 2a.

[0008] The address generator 3 a generates address data based on the clock of the timing generator 13 and sends it to the pattern memory 7. The pattern memory unit 7 sends out the data written in the pattern memory unit 7 corresponding to the address data generated by the address generation unit 3a to the format unit 9. The format unit 9 includes a pattern memory unit 7
Is formed into a predetermined waveform, and is applied to the DUT 12 via the pin electronics unit 10.

After the execution of the test pattern A is completed, the control section 1a opens the above-mentioned relay. Next, the control unit 1a executes “TEST“ B ”” and “TEST” of the test program.
The same processing as “TEST“ A ”” is performed on the test patterns B and C for the instruction “C” ”. FIG. 3C shows this series of processing over time.

[0010]

The above-described conventional IC tester uses a test pattern under the control of a control unit.
Each time the UT is tested, the DC of the pin electronics section
In order to set the level, open and close the relay of the signal path to the pin electronics section and the DUT, and set the top address data of the test pattern stored in the test pattern memory section to the address control section, a plurality of test patterns When the continuous test is executed without changing the DC level using the method, there is a drawback that the setting process for the number of tests is required and the test time becomes long.

An object of the present invention is to provide an IC tester with a short test time.

[0012]

Means for Solving the Problems The constitution of the present invention comprises a pattern
Read multiple test patterns stored in the memory
Tests the IC under test connected to the electronics
In the case of performing a continuous test using the plurality of test patterns without resetting the voltage levels of the driver and the comparator of the pin electronics unit in the IC tester ,
A control unit having means for prohibiting the opening and closing of the relay signal path to resetting said IC to be tested of the pin electronics section of the voltage after test Topatan completion, the plurality of controlling the generation of the test pattern to be tested Address control units, and are connected and executed corresponding to these address control units
It includes a plurality of address generator for generating an address, and a switching unit switching the connection between the pattern memory section and these multiple <br/> number of address generator, the plurality of address generators
By sequentially switching the outputs of the
To be tested continuously.
You.

[0013]

Next, the present invention will be described with reference to the drawings. FIG. 1A is a block diagram of a pattern generating mechanism according to a first embodiment of the present invention. FIG. 1B is a time chart of a processing operation inside the IC tester at the time of a continuous test using a plurality of test patterns. 1A is a control unit in the IC tester 20, 3 is a main address generation unit, 4 is a sub address control unit,
5 is a sub-address generation unit, 6 is a switching unit, 7 is a pattern memory unit, 8 is a timing generation unit, 9 is a format unit, 1
0 is a pin electronics section connected to the DUT.

When the test program shown in FIG. 3B is executed, the control unit 1 in the IC tester 20 sends a test pattern A to the main pattern address control unit 2 and the sub pattern address control unit 4 in advance. , B of the test pattern memory unit 7 are allocated and set, and transmitted.

The control unit 1 includes a pin electronics 1
Then, the DC level inside 0 is set, and the relay of the signal path between the pin electronics unit 10 and the DUT 12 is closed to be electrically connected. The main address control unit 2 controls the traveling of the test pattern A under the control of the control unit 1. The sub address control unit 4 waits until the execution of the test pattern A is completed.

After the execution of the test pattern A, the control unit 1
The relay between the pin electronics unit 10 and the DUT 12 is not opened or closed.
A test by a test pattern B is instructed, and switching control is performed on the switching unit 6 so that the address data of the sub address generating unit 5 is transmitted to the pattern memory unit 7.

The sub address controller 4 controls the sub address generator 5 to generate a test pattern B. The control unit 1
During the execution of the test pattern B, the start address data of the pattern memory unit 7 of the test pattern C to be executed next is set in the main address control unit 2 and the pattern generation processing is waited until the execution of the test pattern B is completed.

After the execution of the test pattern B, the control unit 1
The reset of the C level of the pin electronics unit 6 and the opening / closing of the relay of the path are not performed, but the test is immediately instructed to the main address control unit 2 by the test pattern C. Switching control is performed so that data is transmitted to the pattern memory unit 7.

The main address controller 2 controls the main address generator 3 to generate a test pattern C. The control unit 1
After execution of test pattern C, pin electronics section 1
The relay between 0 and the DUT 12 is cut off to end the continuous test using the plurality of test patterns.

FIG. 2 shows a second embodiment of the present invention, in which a data holding unit 11 is provided between a format 9 and a pin electronics unit 10. If the total test pattern capacity used for testing is larger than the test pattern memory capacity, all test patterns cannot be stored in the test pattern memory, so the test pattern to be executed is stored in a buffer memory other than the test pattern memory, and the test pattern to be executed is buffered. The test pattern memory is read from the memory and executed.

During the reading time, the data holding unit 11 holds the test pattern data applied immediately before in order to prevent the signal to the DUT from changing or becoming indefinite during execution of the test pattern.

[0022]

According to the IC tester of the present invention, when a continuous test using a plurality of test patterns is executed without changing the DC level of the pin electronics section, the control of the control section controls the pin electronics section after the end of the test pattern. D
The setting of the C level, the opening / closing of the relay of the signal path to the pin electronics unit and the DUT are prohibited, and the leading address data of the test pattern of the test pattern to be executed in advance is assigned to a plurality of pattern address control units. Since the test pattern generation is controlled alternately, the setting of the DC level of the pin electronics section after the test pattern is completed, the opening / closing processing of the relay of the signal path to the pin electronics section and the DUT, and the address setting processing of the test pattern to be executed next are performed. By omitting it, the test time can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are a block diagram and a time chart for explaining an operation of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIGS. 3A to 3C are a block diagram of an example of a conventional IC tester, a partial diagram of a test program for explaining the operation, and a time chart, respectively.

[Explanation of symbols]

 Reference Signs List 1 control section 2 main address control section 3 main address generation section 4 sub address counter section 5 sub address generation section 6 switching section 7 pattern memory section 8 timing generation section 9 format section 10 pin electronics section 11 data holding section 12 DUT 20 IC tester

Claims (1)

(57) [Claims] A plurality of test patterns stored in a pattern memory unit;
Button and read out the object connected to the pin electronics section.
In IC tester for testing of the test IC, re the case of not reconfigure the pin electronics section the driver and the comparator voltage level of testing continuous by the plurality test pattern, the pin electronics of the voltage after test Topatan completion A control unit having means for prohibiting setting and opening / closing of a relay in a signal path to the IC under test
When a plurality of address controller for controlling the generation of the test pattern to be tested, corresponding to these address control unit
Generating a connected address to be executed Te has a plurality of address generator, and a switching unit switching the connection between these and the plurality of address generator and the pattern memory section, wherein
By sequentially switching the outputs of a plurality of address generators
So that the plurality of test patterns are continuously tested.
IC tester, characterized in that the.