JPS6468122A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

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Publication number
JPS6468122A
JPS6468122A JP62227401A JP22740187A JPS6468122A JP S6468122 A JPS6468122 A JP S6468122A JP 62227401 A JP62227401 A JP 62227401A JP 22740187 A JP22740187 A JP 22740187A JP S6468122 A JPS6468122 A JP S6468122A
Authority
JP
Japan
Prior art keywords
output terminal
gate
drain
delay time
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227401A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakazato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62227401A priority Critical patent/JPS6468122A/en
Publication of JPS6468122A publication Critical patent/JPS6468122A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To decrease the propagation delay time of each stage by connecting a source or a drain of one conduction type MOS transistor(TR) to an output terminal, connecting one drain or source to a fixed potential wire respectively and connecting a gate to an intermediate terminal between complementary MOS gates placed at the pre-stage than the output terminal. CONSTITUTION:The gate width W of each TR in inverse amplifiers 1-3 using complementary MOS TRs is formed to be larger sequentially. A source S of an N-channel MOS TR 4 having a capacity (100mum or over) enough to charge a load capacitor CL connecting to an output terminal OUT of the inverse amplifier 3 is connected to an output terminal, the drain D is connected to a power terminal VDD and the gate G is connected respectively to an output terminal M1 of the inverse amplifier 1. Since the gate G of the N-channel MOS TR 4 is connected directly to the output terminal of the amplifier 1, the propagation delay time tp' in the presence of the TR 4 is decreased in comparison with the propagation delay time tpd when no TR 4 is employed (in a conventional example).
JP62227401A 1987-09-09 1987-09-09 Semiconductor integrated circuit device Pending JPS6468122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227401A JPS6468122A (en) 1987-09-09 1987-09-09 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227401A JPS6468122A (en) 1987-09-09 1987-09-09 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6468122A true JPS6468122A (en) 1989-03-14

Family

ID=16860251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227401A Pending JPS6468122A (en) 1987-09-09 1987-09-09 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6468122A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843622A (en) * 1981-09-09 1983-03-14 Hitachi Ltd High-speed driver circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843622A (en) * 1981-09-09 1983-03-14 Hitachi Ltd High-speed driver circuit

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