JPS646568B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for outputting arbitrary pulses in a computer-based device.

In output interface circuits of microcomputers or output circuits for engine control such as fuel injection pulses and ignition signals, it is required to output pulses with arbitrary pulse width, period, and arbitrary delay time from a predetermined point. be done.

As a conventional pulse output device, for example, a block diagram is shown in FIG. 1, and a signal waveform diagram is shown in FIG. 2.

In FIG. 1, 1 is a register for setting the pulse width, 2 is a comparison circuit, 3 is a counter, and 4 is a flip-flop.

First, write an arbitrary setting value (pulse width) into register 1. Next, the counter 3 is controlled by the reference pulse S ₁ .
and at the same time set flip-flop 4 (output _S6 is inverted).

Counter 3 counts clock pulses _S2 from the moment it is reset.

Comparison circuit 2 compares output S ₃ corresponding to the setting value of register 1 and output S 4 of counter 3, and S ₄ is compared with _{S 3}
When the value exceeds the value, the signal _S5 is output. This signal _S5 resets the flip-flop 4 and inverts the output _S6 again.

Therefore, the output S ₆ is a pulse having a pulse width τ 1 from the time T ₁ when the reference pulse S ₁ is applied to the time T ₂ when the count value S ₄ of _the counter 3 reaches the set value. Although S ₃ and S ₄ in FIG. 2 are originally digital signals, they are shown in analog form for convenience of display.

Further, in order to output a pulse with an arbitrary delay time from a predetermined time point, for example, a block diagram is shown in FIG. 3, and a signal waveform diagram is shown in FIG. 4.

In FIG. 3, two registers 1' and 1'', two comparators 2' and 2'', and two counters 3' and 3'' are used.Then, a value corresponding to the delay time is written to register 1', and register 1'' is used. Write the value corresponding to the pulse width to . Further, the flip-flop 4 is set by the signal _S'5 of the comparison circuit 2', and reset by the signal _S''5 of the comparison circuit 2''.

With the above configuration, as shown in FIG. 4, the reference pulse S ₁ rises at time T ₄ , which is a delay time τ ₂ after the time T ₃ when it is applied, and at time T ₅ , after a pulse width τ ₃ . A falling output S ₆ is obtained.

However, in the conventional device as described above, only one pulse can be output for one reference pulse, and in order to output multiple pulses for one reference pulse, multiple sets of the above configuration are required. shall be. Furthermore, in a device with a delay time as shown in Figure 3, two sets of counters, comparators, and registers are required for one pulse.
When trying to output a plurality of pulses, there was a problem in that the device became complicated and expensive.

The present invention was made in order to solve the above problem, and is a means of expressing time by free-running a counter without resetting it, and by sequentially setting the time at which the output is to be changed in a comparison register. It is an object of the present invention to provide a method of outputting a plurality of arbitrary pulses by changing the output when the value of the counter matches the value of the counter.

The present invention will be explained in detail below based on the drawings.

FIG. 5 is a block diagram of one embodiment of the present invention, and FIG. 6 is a first signal waveform diagram of the method of the present invention.

In FIG. 5, 5 is a free running counter that continuously counts clock pulses _S2 , and 6 is a free running counter that continuously counts clock pulses S2.
7 is a comparison register, 7 is a central processing unit (hereinafter referred to as CPU) of the microcomputer, and 8 is an output port within the CPU.

First, the CPU 7 is interrupted by a reference pulse S ₁ that is generated when a certain event occurs, and the count value N ₇₁ of the free running counter 5 at that time T ₆ (the value of the output S ₇ at time T ₆ ) is calculated. Load. At the same time, the output of output port 8
Invert S ₁₀ . Further, a calculation is performed to add a value corresponding to the desired pulse width to the read value N ₇₁ , and the value N ₈₁ resulting from the calculation is applied to the comparison register 6 as a signal S ₈ , and N ₈₁ is written into the comparison register 6 . Note that _M6 in FIG. 6 indicates the contents of the comparison register 6.

Next, as time passes, the output _S7 of the free running counter 5 increases, and when its value reaches the aforementioned _N81 , the comparison register 6 outputs the signal _S9 .
This signal S ₉ interrupts CPU 7 and outputs S ₁₀
Invert.

Therefore, the output S ₁₀ becomes a pulse that rises at time T ₆ when the reference pulse S ₁ is applied and falls at time T ₇ after a desired pulse width τ ₄ .

Furthermore, if the above operation is repeated and the output line of the output port 8 is switched each time, multiple pulses S _10-1 , S _10-2 , S _10- can be generated for one event (one reference pulse). ₃ can be extracted from multiple output lines (details will be explained later).

Further, for events that occur continuously at a fixed period or an irregular period, a plurality of pulses can be extracted from a plurality of output lines.

Next, the case of outputting a pulse with a delay time will be explained.

As shown in the signal waveform in Fig. 7, the CPU 7 is first interrupted by the reference pulse _S1 , and the count value _N72 of the free running counter 5 at that time _T8 (the value at the time _T8 of the output _S7 ) is calculated. Load. A value corresponding to the delay time width is added to the read value _N72 , and the resultant value _N82 is set in the comparison register 6.

Thereafter, as time passes, the output _S7 of the free running counter 5 increases, and its value becomes the aforementioned _N82.
When reached, the comparison register 6 outputs the signal _S9 . This signal _S9 interrupts the CPU 7 and transfers the contents of another register (not shown) to the output port 8, thereby inverting the output _S10 and inverting the contents of the register.

Next, a value corresponding to the desired pulse width is added to the value N ₈₂ written in the comparison register 6, and the value N ₈₃ resulting from the calculation is written in the comparison register 6.

When the output S ₇ of the free-running counter 5 rises further and reaches the value N ₈₃ mentioned above, the comparison register 6 outputs the signal S ₉ again. By this signal S ₉
The CPU is interrupted and the contents of the inverted register are transferred to the output port 8, thereby inverting the output _S10 .

Therefore, the output S ₁₀ becomes a pulse that rises at time T 9 delayed by the delay time _{τ 5} from time T ₈ when the reference pulse S ₁ is applied, and falls at time T ₁₀ after the desired pulse width τ ₆ . .

Next, a case where the free running counter 5 overflows will be explained.

When the count value reaches the maximum count value, the free running counter is automatically reset and starts counting again from the beginning. Therefore, if the desired value of the delay time or pulse width is large and there is a risk that the free-running counter 5 will overflow, it is necessary to take this into consideration.

For example, as shown in the signal waveform in Fig. 8, first interrupt the CPU 7 with the reference pulse _S1 ,
The count value _N73 of the free running counter 5 at that time _T11 (the value at time _T11 of the output _S7 ) is read.

Next, the free running counter 5 counts the clock pulses _S2 , and when an overflow occurs, a carry signal _S11 is output. Every time this carry signal _S11 is given, an interrupt is issued to the CPU 7, and the number of overflows is counted. When the number reaches a predetermined number, an interrupt is issued to the CPU 7, and the maximum count value of the free running counter 5 multiplied by the number of overflows is subtracted from the value corresponding to the desired delay time width (or pulse width). An operation is performed to add the value to the read value N ₇₃ , and the value N ₈₄ as a result of the operation is written into the comparison register 6.

Next, when the output S ₇ of the free running counter 5 rises and matches the content N ₈₄ of the comparison register 6, the CPU 7 is interrupted and the content of another register (not shown) is transferred to the output port 8. Inverts the output _S10 and inverts the contents of its register.

In other words, if the value equivalent to the delay time width (or pulse width) is N, the number of overflows is n, the maximum count value of the free running counter is a, and an arbitrary number is b, then the delay time width N is N = na + b. expressed. By appropriately selecting n and b, an arbitrary delay time width can be set. Note that the pulse width can also be set to a value that takes similar overflow into account, so it is possible to freely output pulses with a delay time width or pulse width longer than the maximum count value of the free running counter.

Next, FIG. 9 is a signal waveform diagram when a plurality of arbitrary pulses are output for one event (one reference pulse).

First, when the reference pulse S ₁ is applied, an interrupt is issued to the CPU 7, and all outputs S _10-1 to S _10-5 of the CPU 7 are inverted. Further, the count value N ₀ of the free running counter 5 at that time is read, and a value N _a obtained by adding a value corresponding to the pulse width τ _a of the output S _10-1 to that value is written in the comparison register 6.

When the output S ₇ of the free running counter 5 rises to match N _a , the comparison register 6 outputs a signal S ₉ . This signal _S9 interrupts the CPU7,
Invert output _10-1 . At the same time, a value N _b corresponding to the pulse width τ _b of the output S _10-2 is written into the comparison register 6.

When the output S ₇ of the free running counter 5 matches N _b , the output S _10-2 is inverted in the same way as above,
At the same time, a value N _c corresponding to the pulse width τ _c of the output S _10-3 is written into the comparison register 6.

By repeating the same operation, any pulse width τ _a , τ _b , τ _c , τ _d , τ _e can be obtained from one reference pulse.
A plurality of pulses S _10-1 to S _10-5 can be output.

Note that the processing when the free running counter 5 overflows is the same as the case in FIG. 8 above.

As described above, according to the present invention, a plurality of arbitrary pulses can be output for one event (one basic pulse), and the configuration can be simplified.

[Brief explanation of the drawing]

Fig. 1 is an example of the conventional device, Fig. 2 is the signal waveform diagram of Fig. 1, Fig. 3 is another example of the conventional device, Fig. 4 is the signal waveform diagram of Fig. 3, and Fig. 5 is the signal waveform diagram of Fig. 1. The block diagram of one embodiment of the present invention and FIGS. 6-9 are signal waveform diagrams of the method of the present invention, respectively. Explanation of symbols, 1, 1', 1''...Register, 2,
2', 2''...comparison circuit, 3, 3'33''...counter,
4...Flip-flop, 5...Free running counter, 6...Comparison register, 7...CPU, 8...Output port.

Claims (1)

[Claims] 1 A microcomputer, a comparison register,
A free-running counter that continuously counts clock pulses of a fixed period, and inverts the output of the output port of the microcomputer when a reference pulse that occurs when a predetermined event occurs is applied. , read the value of the free running counter at that time into the microcomputer, add a value corresponding to the desired pulse width to the read value, write the added value to the comparison register, and compare it with the written value. When the value of the free running counter matches the value of the free running counter, the output of the microcomputer is inverted again, and the above reading, addition, writing, and output inversion operations are repeated, and the output line of the output port is changed each time. A pulse output method characterized by outputting a plurality of pulses each having a desired pulse width for one event from a plurality of output lines by switching.