JPS6117181B2 - - Google Patents

Description

Detailed Description of the Invention For example, when 8-bit serial data pulses are taken into an 8-bit shift register, the supply of clock pulses to the shift register must be stopped when all of the data pulses are taken into the shift register. , the data pulse is pushed out of the shift register.

In this case, if the data pulse itself has clock information, it is possible to prevent the data pulse from being pushed out by stopping the supply of the clock pulse to the shift register when the data pulse ends. In the case of a signal, it does not have clock information, and only the time interval of each bit and the number of bits handled at one time are specified, so the above method cannot be used.

Therefore, a circuit for taking such data pulses into a shift register is generally constructed as shown in FIG.

That is, in FIG. 1, 1 is a data pulse input terminal, 2 is a shift register, 3 is a decoder, and 4 is a clock pulse forming circuit. The data pulse supplied to terminal 1 is then
As shown in, for example, a 9-bit serial pulse Pd
However, the first bit is a guide bit that heralds the arrival of this data pulse Pd and is always "1", and the following second to ninth bits have information.

When this data pulse Pd is supplied to terminal 1, this causes the RS flip-flop circuit 5 to
is set and the pulse is set as shown in Figure 2B.
The flap signal Sf rises at the first bit of Pd, and therefore the data pulse Pd is supplied to the register 2 through the AND circuit 6. Also at this time,
When the signal Sf rises, a clock pulse Pc synchronized with the pulse Pd is supplied from the forming circuit 4 to the register 2 through the AND circuit 7, as shown in FIG. 2C. Therefore data palace Pd
are sequentially fetched into the register 2, for example, every time the clock pulse Pc rises.

At this time, the number of clock pulses Pc being supplied to the register 2 is counted by the counter 8, and when the number of clock pulses Pc reaches 9, that is, when the 9-bit data pulse Pd is input into the register 2, , counter 8
The flip-flop circuit 5 is reset through the decoder 9 by the count value of , the signal Sf falls, and the clock pulse Pc is no longer supplied to the register 2.

Thus the data pulse Pd for register 2
The contents of register 2 are supplied to decoder 3.

In this case, the counter 8 counts the number of clock pulses Pc supplied to the register 2 and ensures that only the required number is supplied.
The data pulse Pd is neither pushed out of the register 2 nor left behind.

However, such a capture circuit requires a counter 8 and a decoder 9 having a counting capacity equal to the number of bits of the data pulse Pd, which increases the cost and cannot be used in low-cost equipment, for example.

Therefore, the present invention aims to provide a low-cost acquisition circuit that does not require the counter 8 and decoder 9.

An example of this will be explained below.

In FIG. 3, the shift register 2 has 8 bits corresponding to the number of bits of information of the data pulse Pd. As shown in FIG. 4A, the data pulse Pd from the input terminal 1 is supplied to the set terminal S of the RS flip-flop circuit 5, and the flip-flop circuit 5 is set by the rising edge of the first bit of the pulse Pd. As shown in FIG. 2B, a signal Sb is taken out from its output terminal, which falls at a time _t2 , which is slightly delayed from the rise time _t1 of the first bit of the pulse Pd.
Then, this signal Sb is supplied to the AND circuit 11, and the pulse Pd from the terminal 1 is supplied to the AND circuit 11, and the pulse Pd from the AND circuit 11 is outputted from the AND circuit 11 during the period _t1 to _t2 , as shown in FIG. 4C. The pulse Pr that has been rising for only a certain period of time is taken out, this pulse Pr is supplied to the clear terminal C of the register 2, and the register 2 is cleared at time _t1 .

Further, as shown in FIG. 4D, from the Q output terminal of the flip-flop circuit 5, a flag signal Sf that rises at time _t2 , contrary to the signal Sb, is taken out.
This signal Sf is supplied to the clock pulse forming circuit ₄ , and as shown in FIG. At the same time, the data pulse Pd from the terminal 1 is supplied to the input terminal of the register 2. Therefore, register 2 receives a data pulse at each rising edge of clock pulse Pc from time _t2 .
Start taking in Pd.

Then, as the data pulse Pd is taken in, and at time _t3 when the clock pulse Pc rises for the 8th time, the 8th bit of the data pulse Pd is taken into register 2, but since register 2 has 8 bits, this At this time, the first bit of the first fetched pulse Pd is pushed out of the register 2, and the output signal Sr of the register 2 rises from time _t3 , as shown in FIG. 4F.

This signal Sr is then supplied to the AND circuit 12, and the clock pulse from the forming circuit 4 is also supplied to the AND circuit 12.
Pc is supplied to the AND circuit 12 through the inverter 13, and from the AND circuit ₁₂ , as shown in _{FIG .} Next, at time _t5 when the clock pulse Pc rises, a falling signal Sa is taken out, and this signal Sa is supplied to the differentiating circuit 14, and as shown in FIG.
The differential pulse Pb of the falling edge of Sa is taken out at time _t5 , and this pulse Pb is supplied to the reset terminal R of the flip-flop circuit 5 through the inverter 15. Therefore, the time point is slightly later than time t ₅ .
At _t6 , the signal Sb rises and the signal Sf falls, which also causes the clock pulse Pc to stop.

However, since the clock pulse Pc has risen at time _t5 , the clock pulse Pc has risen nine times during the period _t1 to _t6 , and therefore the register 2 has the data pulse Pd rising nine times. This means that the bit has been incorporated. Since register 2 has 8 bits and the information bits are the 2nd to 9th 8 bits of the data pulse Pd, at time _t5 , these 8 information bits are the same as in register 2. This means that it has been taken in. The contents of this register 2 are then decoded by a decoder 3.

In this way, the acquisition of one set of data pulses Pd is completed, but in this case, according to the present invention, the counter 8 and decoder 9 for counting the number of clock pulses Pc are not required, and the cost can therefore be reduced. This also allows it to be used in low-cost equipment. Especially data pulse
As the number of bits of Pd increases, in the circuit of Fig. 1,
Since the number of stages of the counter 8 and the decoder 9 increases, it is extremely effective in such a case.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of a conventional example, Fig. 2 is a waveform diagram for explanation thereof, and Fig. 3 is a system diagram of an example of the present invention.
FIG. 4 is a waveform diagram for explaining this. 2 is a shift register, and 4 is a clock pulse forming circuit.

Claims (1)

[Claims] 1. In a circuit that does not have clock information, but in which the first bit is used as a guide bit, and the entire data pulse has a constant number of bits is taken into a shift register, the shift register has a fixed number of bits of the data pulse. The number of bits is one bit smaller than an AND circuit that forms a clear pulse for clearing the shift register using the output of the RS flip-flop and the input first bit; and a clock pulse forming circuit that is controlled by the output of the RS flip-flop and provides a shift lock to the shift register. Configured data pulse acquisition circuit.