JPS6465655A - Memory interface control system - Google Patents
Memory interface control systemInfo
- Publication number
- JPS6465655A JPS6465655A JP22187087A JP22187087A JPS6465655A JP S6465655 A JPS6465655 A JP S6465655A JP 22187087 A JP22187087 A JP 22187087A JP 22187087 A JP22187087 A JP 22187087A JP S6465655 A JPS6465655 A JP S6465655A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- signal
- timing signal
- access
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To minimize the suppressing time of a memory access command at the time of generating a write request signal to a memory and to prevent the generation of a malfunction, by providing the titled system with a memory access command means and a suppressing means. CONSTITUTION:In case of writing data in a memory, the data are written in a buffer storage part 4 synchronously with a clock signal. An address timing signal and a data timing signal are respectively generated from an address timing signal generating means 2 and a data timing signal generating means 3 synchronously with said writing in the storage part 4. When the clock signal is not stopped, the memory access commanding means 6 sends an access commanding signal quickly to the memory synchronously with the address timing signal. When the clock signal is stopped during the generation of the data timing signal, the suppressing means 5 suppresses the output of the access commanding signal from the means 6 to the memory to inhibit memory access during the stop of the clock signal. Consequently, the access time can be shortened and the generation of the malfunction can be prevented.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22187087A JPS6465655A (en) | 1987-09-07 | 1987-09-07 | Memory interface control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22187087A JPS6465655A (en) | 1987-09-07 | 1987-09-07 | Memory interface control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6465655A true JPS6465655A (en) | 1989-03-10 |
Family
ID=16773470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22187087A Pending JPS6465655A (en) | 1987-09-07 | 1987-09-07 | Memory interface control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6465655A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04140880A (en) * | 1990-10-02 | 1992-05-14 | Nec Corp | Vector processor |
-
1987
- 1987-09-07 JP JP22187087A patent/JPS6465655A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04140880A (en) * | 1990-10-02 | 1992-05-14 | Nec Corp | Vector processor |
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