JPS646486B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a method for writing digital data into memory through processing by a central processing unit (CPU), even though the same address bus is used. The present invention relates to a data processing circuit that allows data to be written during a period when a corresponding image is being reproduced, and that reduces data transfer time.

"Technical Background of the Invention" Teletext broadcasting is an example of a system that writes data into a memory through processing by a CPU and processes the written data.

Teletext broadcasting is a broadcasting system in which digital signals are multiplexed and transmitted during the vertical retrace period of a television video signal, and image information consisting of characters and graphics is displayed on a receiver.

In this teletext broadcast, the image data transmitted during the vertical retrace period is written into an image memory via the CPU, and read out during the screen display period to obtain a reproduced image.

Conventionally, the transmitted image data is transmitted during a so-called non-display period when an image corresponding to the transmitted data is not reproduced on the reproduction screen. During the image display period, image data is read from the image memory and reproduced and displayed.

In this case, if the image is a color image, color signal information is transmitted in addition to the image data corresponding to the luminance signal.

Incidentally, one page of the reproduced screen is usually divided into display sections called blocks and sub-blocks, and coloring is performed using these sections as units.

Note that the reproduced pixels are divided into, for example, 248 horizontally and 204 vertically, and the sub-block serving as the unit area for coloring is an area of 8 (horizontal) pixels x 12 (vertical) pixels.

By specifying a color for each sub-block, coloring of the corresponding portion in the reproduced image is specified.

In order to display the reproduced image in color in this way, an image memory that holds image data corresponding to the luminance signal and a color memory that holds coloring data for the above-mentioned sub-block areas are required, and the data in these memories is processed by the CPU. A reproduced image can be obtained by accessing.

In this case, data is written into the memory during a non-display period when image data is not displayed.

For this reason, when processing image data and colored data, it is necessary to determine the non-display period and display period, and to specify the access timing, which may result in poor data read/output transfer efficiency. I have no choice but to.

``Problems with the background technology'' In other words, conventionally, when reproducing and displaying transmitted image data such as teletext broadcasting, in order to transfer data from the CPU to the image memory and color memory, the access was limited to non-conventional periods such as the vertical blanking period. This was done using the display period.

For this reason, the CPU must detect that it is a non-display period, and a means of detection is required for this purpose. Also, since data can only be transferred during the non-display period, the data transfer speed may be slow. The problem is that it is unavoidable.

Furthermore, when DRAM (dynamic RAM) is used as image memory and color memory, the address is divided into two parts: row address (RAS) and column address (CAS), and address signal access is performed. RAS and CAS control are required to latch the row address and column address, and the CPU and
It is difficult to connect DRAM directly.

For this reason, it is common practice to store the address signal in a separate register or the like and provide it to the memory together with the RAS and CAS discrimination control signals.

In this case, the address must be transferred to the address register each time data is written to or read from the memory.

As a result, in addition to data being transferred only during the non-display time, address transfer efficiency is poor, and data access time is slow, which has been a problem in the past.

To illustrate this conventional problem using the case of teletext broadcasting as an example, as shown in Fig. 1, the display period signal (Fig. 1 a) is detected by the CPU, and during this period 8/
Every four clocks of the clock signal (FIG. 1b) with a frequency of 5fsc (fsc color subcarrier frequency), a gate signal for colored data (FIG. 1c) is generated, and an image data gate signal (first Figure d) is generated.

As a result, only during the display period (FIG. 1a), access is made to read image data and coloring data from the image memory and color memory, respectively, and screen display is performed.

In other words, during the display period (FIG. 1a), only data can be read, and neither image data nor colored data is written into the memory.

Data is only written when the CPU detects a non-display period.

In such data access, data writing is limited to the non-display period, so there is a problem in that it takes time to access the data.

"Purpose of the Invention" This invention has been made to address the above-mentioned difficulties. When processing data such as image data of teletext broadcasting, etc., data writing is not limited to the non-display period of the image, but can be performed during the display period. The purpose is to make it possible to write data to other devices, thereby reducing data transfer time.

Furthermore, the present invention performs an automatic address increment operation without controlling switching between upper and lower addresses for each data, thereby shortening access time for address specification and improving data transfer efficiency regarding data processing. The purpose is to improve.

"Summary of the Invention" Therefore, in this invention, a data access gate period is provided in addition to the coloring data gate period and the image data gate period in the image display period, and even though it is a display period, the access gate period is It is possible to access the memory to write coloring data, image data, etc.

This enables data access other than data reading between the CPU and memory during the display period, reducing data access time.

Further, when specifying an address, if a starting value address is given, the address is automatically incremented each time data is transferred, thereby reducing data access time as much as possible.

"Embodiments of the Invention" Hereinafter, embodiments in which the present invention is applied to a teletext receiver will be described with reference to the drawings.

Generally, a display screen for teletext broadcasting is configured as shown in FIG.

That is, as shown in the same figure, in the horizontal direction of the screen there are 0 to
An X address of 31 (including buffer portion) is attached,
Y addresses from 0 to 215 (including the buffer) are assigned in the vertical direction.

The Y address shown here is an address for each line, and is an address for a unit pixel in the vertical direction of image data.

In addition, since it is subdivided into 31×8=248 in the horizontal direction, the unit display pixel of the image data has the size of one line divided into 248 equal parts in the horizontal direction and the thickness of one line in the vertical direction.

On the other hand, in the coloring data, the shaded area (sub-block) in FIG. 2 is a unit coloring area.

Therefore, one unit of the Y address of the colored data is 12 lines with respect to the Y address of the image data.

By the way, when a reproduced image is constructed in the form shown in FIG. 2, data for one screen is comprised of approximately 8K bytes of data.

In this case, 13 bits are required for the address.

Here, the 16-bit addresses of the memory for storing image data and colored data are time-divided in 8-bit units.

As mentioned above, 13 bits are enough to specify the address for one screen, but in this example, when transmitting the row address (RAS), 8 bits of data are transferred by adding 3 bits as a dummy to the 5 bits of the address signal. , the remaining 8-bit address signal is used as a column address (CAS) for transfer.

The 5-bit RAS signal mentioned above is shown in Figure 2.
The 8-bit CAS signal corresponds to the X address (0 to 31) in the horizontal direction of the configuration screen, and the Y address (0 to 215) in the vertical direction.

The designation of the X address and Y address for these component screens, that is, the transfer of the RAS signal and CAS signal, is performed at the timing shown in Figure 3, and when accessing the colored signal, the colored data gate signal,
A major feature of the present invention is that an access gate signal is generated after the subsequent image data gate signal is generated, and data can be accessed during this period as well.

To explain the outline of the present invention using FIG. 3, it is assumed that data is read from the memory and an image is displayed during the display period (FIG. 3a).

At this time, 8/5fsc (fsc: color subcarrier frequency)
During 3 clocks (T ₁₁ ) of the frequency clock (Figure 3b), 5-bit RAS and 8-bit CAS
The X address is transferred as a signal and colored data is read from the corresponding address (FIG. 3c).

Furthermore, during the period indicated by _T21 in FIG. 3c, the image data is read out after upper and lower addresses are specified by the RAS and CAS signals similarly to the colored data (FIG. 3d).

In this way, the reading of the colored data and image data is completed in 6 bits (6 clocks) of 1 byte period (8 clocks of 8/5 fsc) during the display period shown in FIG. 3A.

In this invention, during one byte period of data (8/
Coloring data of 8 clocks of 5fsc), 2 bits of image raw data readout end (2 clocks of 8/5fsc), and 4 bits of 2 bits after the start of the next 1 byte period (4 clocks of 8/5fsc) ) is provided with an access gate signal (FIG. 3e).

A 4-bit period is provided in the 2-byte period (16 clocks of 8/5 fsc) of this display period (Figure 3a), and during this period, data used for image superimposition, etc., in addition to reading the original data. It is possible to read data from memory or write data to memory.

That is, a major feature of the present invention is that data can be written and read as necessary without distinguishing between non-display and display periods of images.

FIG. 4 shows a data processing circuit according to the present invention that allows access between the CPU and memory regardless of whether or not it is an image display period.

In the figure, a portion designated by 100 is an address control portion, and a portion designated by 200 is a portion related to data access.

Also, in the address designation part indicated by 100, 101
102 is a part that controls the address when writing data, and 102 performs control to automatically increment the address value.

Similarly, the address at the time of reading data is specified in the section 103, and the automatic incrementing of the address value is controlled in the section 104.

According to the circuit shown in FIG. 4, it is possible to write or read coloring data or image data during the access gate period shown in FIG. 3e.

Since the value of the address to be accessed is automatically incremented, the time required to change the address can also be reduced.

That is, it has a function of performing an address value automatic increment operation in which the address value is incremented by +1 or +32 each time data is written or read.

In this way, the circuit shown in FIG. 4 has the functions of (1) writing data, (2) reading data, and (3) automatically incrementing the address value during the access gate period shown in FIG. 3e. .

Each of these operations will be explained next.

(1) Data writing In the circuit shown in FIG. 4, the transfer of data from the CPU to the memory, that is, the data writing operation will be explained.

First, by executing an OUT instruction to write data, the leading value of the address to which data is to be written is transferred to write address registers 1 and 2 via address bus AD.

In this case, 13
As mentioned above, among the bit addresses, the X address corresponding to the horizontal direction of the display screen is transferred to register 1, and the Y address corresponding to the vertical direction of the display screen is transferred to register 1.
The address is transferred to register 2. That is,
8 bits (5 bits) transferred to register 1
As shown in Figure 2, the address corresponds to the horizontal address (0 to 31) on the configuration screen, and the 8-bit line address transferred to register 2 corresponds to the vertical address (0 to 125). .

Then, the data to be written to the image memory is transferred to the above address bus AD (address/data bus).
The data is transferred to the write data register 3 via the write data register 3.

At this time, a pulse indicating that the write data has been transferred is sent to the write data access gate flag circuit 4 to set the flag.

When the flag is set in this write data access flag circuit 4, the signal AGF (Access Gate
A write data access gate signal is obtained from the write data access gate generation circuit 5 using the front).

The data transferred to the write data register 3 in this way is stored in the image memory according to the specified address during the write data access period obtained from the first arriving AGF signal (FIG. 3 f, T ₄₁ ). .

The stored data is determined by the write data access gate flag circuit 4 and the write data access gate generation circuit 5.

In this way, the data is written to the image memory during the access period between the CPU and the image memory (period indicated by _T32 in FIG. 3f).

Note that the signal 1P indicated by G in FIG. 3 is a signal for controlling the address value, and the signal indicated by H is a signal for resetting the write data access gate generation circuit 5.

Here, the AGF signal (FIG. 3f) and the reset signal (FIG. 3h), which are signals involved in defining the access period (FIG. 3e), will be explained.

In the circuit shown in FIG. 4, the image display period,
Regardless of the distinction between non-display periods, one access period (one access period for every 2 bytes of data) shown in FIG. 3e is provided between 16 clocks of the 8/5 fsc clock signal.

During this access period, the voltage applied to the write data access gate generation circuit 5 in FIG.
Generated in synchronization with the AGF signal and reset pulse.

The aforementioned write data access flag circuit 4 and write data access gate generation circuit 5 are each constructed of a D-type flip-flop as shown in FIG.

The D terminals of the D-type flip-flops 40 and 50 are kept at a constant potential, and the output Q of the D-type flip-flop 40 is connected to the clock terminal CK of the D-type flip-flop 50 via an AND circuit 51.

The D-type flip-flop 40 uses the write data transfer pulse from the CPU as a clock.
The output is reset by the result of a NAND operation performed by the NAND circuit 41 on the output of the D-type flip-flop 50 at the next stage.

On the other hand, the D-type flip-flop 50 is
The AND circuit 51 performs an AND operation on the output of the type flip-flop and the AGF signal, and the result is used as a clock pulse.

Now, when the address of the image memory to which data is to be written is transferred from the CPU to the write address registers 1 and 2 shown in Figure 4 by the OUT instruction, at this time, the port numbers of the registers 1 and 2 are determined by the address decoder. decoded,
A pulse corresponding to the write enable signal of the CPU is given to the designated register, and the address is taken into registers 1 and 2.

Thereafter, the data to be written to the image memory is transferred to the write data register 3.

At this time, a write data transfer pulse (FIG. 6a) for fetching data into the write data register from the address decoder (not shown) is sent to the terminal _D1 in FIG. 5.

When a write data transfer pulse is applied to terminal _D1 in FIG.
The output terminal Q of becomes "H" level.

When the AGF signal (FIG. 6c) is applied to the AND circuit 51 during the period when the level of this terminal Q is "H" level (FIG. 6b), the level of the output terminal Q of the D-type flip-flop 50 becomes "L". ” level to “H” level (Fig. 6 d).

The output level of the D-type flip-flop 50 is such that the reset pulse (FIG. 6f) obtained from the signal 1P (FIG. 6e) involved in address increment shown in FIG. 6e resets the D-type flip-flop 50. “H” until applied to the terminal
maintain the level.

When a reset pulse is applied to the reset terminal of the D-type flip-flop 50, its output becomes "H".
level changes to “L” level.

As a result, the D-type flip-flop 5 constituting the write data access gate generation circuit 5
A write access gate signal (FIG. 6d) defining a data write access period is generated at the 0 output terminal. (This write access gate signal (FIG. 6d) corresponds to the signal shown in FIG. 3e.) Based on the reset pulse obtained from the AGF signal and the signal 1P, the D-type flip-flop 50
The pulse width of the write access gate generated in is approximately 700μsec, and during this write access gate period, addresses are transferred from write address registers 1 and 2 to the image memory via the MA bus, and data is transferred to the MD. Data is written via the bus.

(2) Reading data Next, the operation of reading data from the CSU for purposes other than the original display during the display period will be described.

Reading data from the memory is performed in substantially the same manner as the write operation, but the read operation differs from the write operation in that reading may be performed as long as the address is transferred.

First, as in the case of a write operation, the address of the image memory to be read is transferred via the CPU to the read byte address shift register 7 and the read line address shift register 8 via the address bus AD by the OUT instruction. be done.

Unlike when writing data, once the address is transferred, data can be read immediately.

The read access gate flag circuit 9 and the read data access gate generation circuit 10 that generate the access gate signal (FIG. 3e) when reading data are the same as those for data writing shown in FIG. It is composed of

Now, when a read line address transfer pulse is applied from the CPU to terminal _R1 , the output Q of the D-type flip-flop that constitutes the read access gate flag circuit 9 goes to the "H" level at the trailing edge of this pulse. Thus, reading of data from the image memory is permitted.

In this way, when the output of the read access gate flag circuit 9 is set to "H",
Similar to the write operation, a reset pulse generated using the AGF and 1P signals (see FIG. 6) described above is applied to the read access gate generation circuit 10.

As a result, a read access gate signal is generated at the output of the read access gate generation circuit 10.

During the access gate period thus obtained, an address is supplied to the address bus, and data to be read from the image memory is transferred to the read data register 11 via the data bus.

Then, the data is transferred by the CPU's IN instruction.
It performs the operation of being read into the CPU via the AD bus.

The IN command in this case corresponds to the read data transfer pulse applied to terminal _R2 in FIG.

Once the data is read into the CPU in this way, in order to read the next data from the image memory to the read data register 11, a read data transfer pulse is applied to the terminal _R2 , and the read access gate flag is set. The output of the circuit 9 becomes "H" level again, and the next data can be read, and data reading continues.

(3) Automatic address increment As mentioned above, data is written or read during the access gate period shown in Figure 3e, but changing the address for each access is done to improve data transfer efficiency. , this embodiment automatically increments the address value.

This automatic incrementing of addresses is done according to the subdivision of the configuration screen shown in FIG.

As shown in FIG. 2, in this embodiment
In the address direction, pixels are subdivided into 32-byte pixels, so if you fix the value of the X address and increase the value of the Y address (vertical direction) by +1,
The address corresponding to the direction) is changed.

On the other hand, if the Y address is fixed and the value of the X address (byte address) in the horizontal direction is increased by +1, the corresponding address in the horizontal direction is changed.

That is, in order to select data to be accessed in the horizontal direction on the configuration screen shown in FIG. 2, it is sufficient to fix the Y address and increase the X address by +1.

Furthermore, to select data in the vertical direction, it is sufficient to fix the X address and increase the Y address by +1.

Incidentally, increasing the Y address by +1 means
Since the pixel is divided into 32 in the X direction, the value corresponds to being incremented by +32 when looking at the address as a whole.

According to such changes in address values, the data to be accessed changes, but the byte address shift register 1 for writing and the byte address shift register 7 for reading that change the address value of the X address are 8-bit shift registers. is used.

Therefore, eight pulses are required to change the address value of the X address.

That is, eight pulse trains are required to change the address value in the X direction.

This pulse train is generated immediately after the reset signal (Fig. 3h) that resets the write access gate generation circuit 5 and the read access gate generation circuit 10 that define the trailing edge of the access gate signal (Fig. 3e). It becomes necessary.

In other words, after a predetermined access is completed during the access gate signal period (Fig. 3e) shown in Fig. 3, the reset pulse (third The above pulse train for changing the X address is generated with the arrival of FIG. h).

This is true for both data writing and data reading.

To change the address value in this way: (1) Detect the generation of the access gate signal and generate a pulse train of pulses having the frequency of 8/5 fsc necessary for changing the X address.

(2) Generation of pulse 1P to change the address value.

Two operations are required.

The pulse train generating circuit 6 shown in FIG. 4 performs these operations, and the details of this pulse train generating circuit 6 are shown in FIG. 7 and its timing chart is shown in FIG. 8 for explanation. .

First, the original pulse 1P that generates the reset pulse (h in Figure 3) used to define the period of the access gate signal is a 1P pulse from the output of an oscillator (not shown) that oscillates at a frequency of 8/5 fsc. Generated by the pulse train generating circuit 30 and generated by the pulse train generating circuit 6
is applied to terminal P ₁ of

The 1P pulse generating circuit 30 generates a pulse every 16 bits (FIG. 8b) from the first pulse of the 8/5 fsc clock (FIG. 8a).

This signal 1P is transmitted to the write access gate generation circuit 5 and the read access gate generation circuit 1.
The reset pulse (FIG. 8c) that defines the trailing edge of the signal period of the access gate signal generated at 0 and applied to the pulse train generation circuit 6 shown in FIG. 7 via terminals P ₂ and P ₃ , respectively. used to generate

That is, the input terminal SI of the shift register 29 shown in FIG. 7 receives the access gate signals (e, d in FIG. 8) applied to the terminals P ₂ and P ₃ and the signal 1P
(FIG. 8b) by the AND circuit 20 (FIG. 8f) is applied.

An 8/5fsc clock (Fig. 8a) is applied to the clock terminal CK of the shift register 29 via the terminal _P4 , and therefore the terminal P on the first stage output terminal _Q1 side of the shift register 29 In ₅ ,
A reset pulse (FIG. 5f, FIG. 8c) for resetting the write access gate generation circuit 5 and read access gate generation circuit 10 is generated.

As a result, the access gate period (Fig. 8d,
e) The trailing edge of e) is determined and the access gate period is determined.

In this way, the pulse train generation circuit 6 shown in FIG.
In addition to generating a reset pulse to determine the access period for writing and reading data, the function also has the function of generating a pulse train for automatically incrementing the address for the next data to be accessed.

This pulse train must be generated in correspondence with the write access gate (FIG. 8d) and the read access gate (FIG. 8e) (FIG. 8g, h).

First, the generation of a pulse train for changing addresses when reading image data will be described.

The read access gate (Fig. 8 e) is generated, and the output of the AND circuit 20 (Fig. 8 f) which performs an AND operation with the signal 1P ₁ (Fig. 8 b) is D.
It is applied to the data terminal D of the type flip-flop 21.

The clock terminal of this D-type flip-flop 21
CK has the above 8/5fsc clock (Figure 8a).
Since the inverted phase of the pulse 1P1 is added to the output terminal Q, a signal obtained by delaying the pulse _1P1 by half a clock of 8/5fsc is obtained.

This signal (FIG. 8i) is ANDed with the read access gate signal (FIG. 8e) applied to the terminal _P2 in the AND circuit 22, and the output of the AND circuit 22 (FIG. 8j) is is used as a set signal for the RS flip-flop 23.

The shift register 29 has an 8-bit configuration, and its final stage output _Q8 is connected to one input terminal of the AND circuit 28, and the 8/5 fsc clock is applied to the other input terminal of the AND circuit 28. .

Therefore, the output of the AND circuit 28 becomes as shown in FIG. 8k, and this signal is used as a reset signal for the RS flip-flop 23.

Therefore, the RS flip-flop 23 is the eighth
It is set by the output signal of the AND circuit 22 shown in FIG. 8J, and reset by the output signal of the AND circuit 28 shown in FIG. 8K.

As a result, a gate signal as shown in FIG. 8l is obtained at the output of the RS flip-flop 23.

This gate signal (FIG. 8l) is applied to the AND circuit 24.
The 8/5 fsc clock is applied to one input end of the clock, and the 8/5 fsc clock is applied to the other input end.

As a result, the output of the AND circuit 24 (terminal
P ₆ ), eight 8/5 fsc clocks are generated immediately after the read access gate period.

The pulse train obtained at the terminal _P6 is transmitted to the 1-bit full adder 12 and the clock switching circuit 14 shown in FIG.
join.

The 1-bit full adder 12 also has the above-mentioned signal 1.
P is added, and the augend data to be added is controlled by the augend data switching circuit 14.

That is, in the configuration diagram shown in FIG. 2, if the address value is incremented by +32 to change the address in the Y direction, it is necessary to change the value of the 8-bit reading line address shift register 8.

Now, when the pulse train shown in FIG. 8g is obtained at the terminal _P6 of the pulse train generating circuit 6, the clock switching circuit 13 controls the addition of the pulse train to the line address shift register 8 for reading.

When a pulse train (FIG. 8g) is applied to the readout shift register 8, the value of the readout line address register 8 increases by +1.

In this increase, only the upper address increases due to the action of the augend data switching circuit 14, and the address value of the upper address is increased by 1, but the address value as a whole is incremented by +32.

When the pulse train is added to the read line address shift register 8 in this way, +1 is added to the previous Y address by the 1-bit full adder 12, and the read line address shift register 8
The address value of the data to be accessed next is set to the address value of the data to be accessed next.

In this way, address values of data to be newly accessed are sequentially set in the vertical direction.

Next, we will discuss the case where the address in the X direction is changed. In this case, the above pulse train (the 8th
Figure h) shows that the read byte address shift register 7 is controlled by the clock switching circuit 13.
applied only to

Therefore, the output of the read byte address shift register 7 increases by +1.

As a result, the address value incremented by +1 is set in the read byte address shift register 7.

As a result, the address in the X direction is incremented.

In this way, address values can be changed in either the X or Y directions without going through the CPU, improving data transfer efficiency.

Although the increment of the address at the time of reading has been described above, the change of the address at the time of writing data is also performed by using the gate timing of the output of the AND circuit 27 in FIG. Pulse train obtained at terminal P ₇ (Fig. 8h)
It is carried out by.

That is, full adder 15, clock switching circuit 16,
The augend data switching circuit 17 increments the addresses in the X and Y directions, as in the case of reading, and sets the address of the data to be written next.

The address thus modified is transferred to the memory via the memory address bus, and the data is accessed via the memory's data bus.

Please note that changes to the above address can be made with +1 or +
Increments of 32 in the X direction or Y
The address is sequentially changed in this direction, but the mode in which the address value is incremented is controlled by addition mode registers 18 and 19.

"Effects of the Invention" As described above, according to the present invention, even during the so-called display period when data to be displayed is being read from the image memory, access for writing data or reading data for purposes other than direct display is prevented. is possible.

As a result, data write access is no longer limited to the non-display period, and data access efficiency is improved.

In addition, when accessing data, the address is not changed for each address via the CPU, but the address is automatically incremented when only the first value address is given, which further reduces data processing time. The present invention provides a data processing circuit for obtaining data.

[Brief explanation of drawings]

Figure 1 is a waveform diagram for explaining the operation of a conventional data processing circuit, Figure 2 is an explanatory diagram for explaining the configuration of a display screen displayed by the data processing circuit, and Figure 3 is a waveform diagram for explaining the operation of a conventional data processing circuit. A waveform diagram for explaining the timing of data processing operation by the data processing circuit according to the invention, FIG. 4 is a circuit diagram showing an embodiment of the data processing circuit according to the invention, and FIGS. FIGS. 6 and 8 are circuit diagrams showing details of the circuit shown in the figure, and waveform diagrams showing timing relationships for explaining the operation of the data processing circuit according to the present invention. 3... Data register for writing, 11... Data register for reading, 4, 5... Access gate signal generation means for writing, 9, 10... Means for generating access gate signal for reading, 5, 6, 1
0...Data access gate signal generation means.

Claims (1)

[Claims] 1. An image memory that stores data to be displayed via a CPU, a display decoder that decodes and displays the image data in the image memory, and stores data to be written in the image memory. a write data register; a write address register that stores the address of the write data; a read data register that stores the data read from the image memory; and a read address register that stores the address of the read data. a register; and when transferring data to be displayed from the image memory to the display decoder during the first and second data read gate periods, after the first read gate signal, from the CPU to the write data register; The first data read gate detects either the transfer of data, the transfer of an address to the read address register, or the read of data in the read data register to the CPU. signal and said second
at least means for generating a data access signal for performing data control on the write register or the read register during a data read signal period of the image memory and the display decoder. A data processing circuit characterized in that data control is performed on the write register or the read data register even during a display period.