JPS6061791A - Display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a display path in a character image information system such as Teletext or Hideotex.

BACKGROUND TECHNOLOGY AND PROBLEMS First, the outline of a general television teletext receiver will be explained with reference to FIG.

In Fig. 1, ′ζ, ill is glta ltd between high frequencies
(2) is a video circuit that performs processing such as color demodulation; (3) is a color picture tube. When receiving normal television broadcasting, the color video signal from the tuner circuit il+ is transmitted to the video circuit (
2), the three primary color signals are extracted, and these signals are supplied to the picture tube (3) to reproduce a color image by broadcasting.

At this time, the color video signal from the tuner circuit (1) is supplied to the synchronous pulse forming circuit IJI+41, and -C=
1ga l+jl 1114 Hals VD, horizontal synchronizing pulse IID, and clock CK are taken out, and the pulses VD and HD are supplied to the deflection circuit (5) to form vertical and horizontal deflection streams 'i1i, which are applied to the picture tube (3). ) is supplied to the deflection coil (6).

In addition, 00) is a microcomputer for reproducing color images from teletext broadcasts, (11) is a CPU with 8-bit parallel processing, and (12) is a program for reproducing color images from teletext broadcasts. RO included
M, (13) is a RAM for the work area, (14) is a keyboard for selecting teletext, etc., (15) is an interface for analog human power, and these circuits (12) to
(15) connects the ζCPU (11) through the system bus (18).
)It is connected to the.

Furthermore, (16) is a display memory, that is, a video RAM that stores display data for one page (one screen) of teletext broadcasting, and (17) forms readout address signals and read signals for display. With a CRT controller,
These are connected to each other and the controller (17
) is connected to the system bus (18). Further, pulses Vo, Ha, and CK are supplied to the controller (17).

Then, when a teletext is selected using the keyboard (14), this is notified to the CPU (11) by an interrupt, and which teletext is required is stored in the RAM (13).

On the other hand, the color video signal from the tuner circuit ill is supplied to the interface (15), the teletext signal in the vertical blanking period is taken out, this signal is once bathed in the interface (15), and the teletext signal is The CPU (11) is informed by an interrupt that the data has been buffered. Then, the CPU (11) checks whether the buffered teletext ta number is the signal of the page selected with the keyboard (14), and ignores it if it is not the signal of the page selected with the keyboard (14). However, the keyboard (1
When it is the signal of the page selected in step 4), the buffered teletext signal is processed by the CPU (11) and passed through the controller (17) to the "ζ video first signal ΔM (
16), and the write address signal and write signal are also sent from the CPtJ (11) to the controller (17).
) is supplied to the RAM (16).

In this way, the display data of the teletext transmission selected with the keyboard (14) is read by the CPU (11) one scanning line at a time.
The data are sequentially written to AM (16).

At this time, a read address signal and a read signal are formed in the controller (17) in synchronization with vertical scanning and horizontal scanning, and these signals 'are supplied to the RAM (16) in a time-sharing manner with respect to the write signal. RAM(
The display data of 16) is sequentially read out in synchronization with vertical scanning and horizontal scanning, and this read display data is decoded by the controller (17) into three primary color signals R, G, B and a luminance signal Y ( Each of the signals R-Y is 1
It is a serial signal of bits, and the total is 4 bits in parallel). These signals R-Y are then supplied to the picture tube (3) through the video circuit (2), so that a color image by teletext is reproduced on the picture tube (3).

Furthermore, when a page is sent via TV teletext,
In standard mode, as shown in Figure 2, one page has 248 horizontal dots x 11204 dots in each field.
It is composed of dots, and eight dots in the horizontal direction are displayed using one byte of display data.

By the way, in such an image information system, the second
For the original screen (page) MN as shown in Figure A,
Insert another screen SB similar to that shown in Figure 2B and synthesize it.
As a result, it is considered to display a composite screen CMP as shown in FIG. 2C. However, in this case, this screen composition is performed using a separate video RAM for the inset screen SH.
This is achieved by combining the signal from the original video RAM (16) with the signal from another video RAM. Furthermore, the size of the embedded screen SH is 64 dots horizontally x 48 dots vertically, and the combining position of the embedded screen SB with respect to the original screen MN is arbitrary, but specified by the transmitting side.

Therefore, for example, if a car is displayed on the inset screen SB,
As well as putting it in place i! By sequentially changing the horizontal position of the jIIIi 118B, a display appears as if a car is moving, that is, a simple moving image can be displayed.

However, in order to display such a composite screen CMP, two counters are required in the receiver to specify the position and vertical position of the water 4 on the inset screen SB. Horizontal atresui, ]
Two counters are also required to generate the number and vertical address signals. Therefore, the receiver must use a large number of counters to control the i+!!! song, and it is also necessary to control its peripheral circuits.
The number of parts used increases, the manufacturing time of the receiver increases, and the cost increases. Furthermore, it is less simple on Zahis.

OBJECT OF THE INVENTION The present invention attempts to solve these problems.

SUMMARY OF THE INVENTION Therefore, in this invention, a counter for determining the horizontal position and vertical position of the inset screen SB and a counter for forming its horizontal address No. 48 and vertical address signal are shared. be.

That is, FIG. 3 does not show one example, and in this example, for the sake of simplicity, the case where a display piece is read out from the video RAM for the embedded screen is not shown. In addition, as shown in FIG. 4, in the composite screen CMP, from the left (A+1
) At the dot and from the top (B+1) Insert into the dot. e7jil! It is assumed that the dot (reference point) at the left corner of l1itliS13 is located.

(21) in Figure 3 shows the video RAM for the inset screen, which has the capacity of address 23; (Address bit) 8Do ``MD2'' is the horizontal address, which is in the range of addresses 10'' to 17'', and the upper address ^D3 to ADs is the vertical address, which is 0.
63, and the remaining shaded area is unused.

In addition, (22) breaks the 8-hit brisettable assemblage down counter and manually sets the preset.

~D7 is supplied with data +1-IJ indicating the horizontal display period of the screen SH from CPLI (II), and its clock input CK is supplied with a clock CK, and its count output Q, o = Q v Medium 3 focus Q3~
Q5 is address AD of RAM (21).

~ to D2 (co-supplied.

Further, (23) and (24) indicate decoders, to which the output Q o '' Q v of the counter (22) and the clock CK are supplied, and the output Q from the decoder (23) is supplied.

To□Qv = r' Output CZR becomes 1" when OJ
is taken out in synchronization with the clock CK, and the decoder (24
), the output CEND which becomes "1" when Qo "Qv = 1'63J" is taken out in synchronization with the clock CK, and these outputs CZR and CEND are sent to the control signal forming circuit (2
5).

This forming circuit (25) generates a control signal ENB which will be described later.

For this purpose, the forming circuit (25) is supplied with a clock CK and a horizontal synchronizing pulse HD, and the controller (17) in FIG. 1 is connected to A and B in FIG. As expected, 1 is set in the period to-ti which is l clocks before the start time t1 of the horizontal display period of the page MN.
'' is supplied. Then, the signal ENB from the formation cycle I!Pt (25) is supplied to the counter (22
The count enable signal M
D is supplied to the count mode manual power U/D of the counter (22), and is also supplied to the output enable manual power OEL of the RAM (21). Further, the signal ST is supplied to the load input LD of the counter (22).

Note that in the vertical direction, illustration and explanation are omitted, but the configuration is similar, and the clock GK and horizontal synchronization pulse H
Instead of D, horizontal synchronization pulse ID and "" are used as surface synchronization pulse vD.

According to such a configuration, when the horizontal display period start time it of page MN is reached, the signal S is output as shown in FIG. 6B.
Since T rises, the CPU (
The horizontal position data rA-IJ from the counter (2)
2), and as shown in ff16 figure C, the counter (22) is loaded at time Li at Qo ”Q? = I-A
Preset to IJ.

Further, when the signal ST falls at the time t1, the signal ENB from the forming circuit (25) is triggered, and ENB="1" is set at the time t1 as shown in the sixth diagram. Furthermore, at this point 1. Smell "C" does not reach No. 6111E and MD="0", so the counter (22) is in the down count mode.

Therefore, the counter (22) starts counting down the clock CK from time 5 and reaches the count value Q.

~Q7 decreases by 1-1'' every clock from 1-A-IJ to C.

Then, when QO-Qv = lOJ at time t2, this is detected by the decoder (23), and as shown in FIG. 25), MD becomes "l" at time L3, one clock after time t2, in synchronization with clock CI ().

Therefore, the counter (22) becomes the amplifier count mode from time t3, and the count value Qo''Qv changes from 0 to 1.
It becomes 11j more popular with each clock.

Then, at time t4, when Qo = Qv -l-63J, this is detected by the decoder (24), and at time t4, as shown in Fig. 6G, it becomes "1" and this signal ( :END is supplied to the formation circuit (25), so all signals are sent to time t5, one clock after time t4, in synchronization with clock GK, and ENB
='“0”, MD-0”, and this state continues thereafter.

In this case, the middle three bits Q3 to Q5 of the count value Qo=Qt are stored in the horizontal address ('jA
As No. AIjo~AD2 (as well as being supplied with
Since the signal MD or the output enable input OE is supplied to the RAM (21), the display data of the horizontal pulses IDO to AD3 of the RAM (21) is changed every 8 clocks during the period from 3 to t5. Each byte is read out sequentially. The period t1 to t3 corresponds to the horizontal section of the head in FIG. 4, and the period t3 to t5 corresponds to the horizontal section of the screen SB in FIG. If processing is performed and display data from RAM (21) is combined with display data from RAM (16),
A composite screen CMP shown in FIG. 4 or FIG. 2C is displayed.

Thus, according to this invention, the inset Mei! lI direction S
, B can be read out for display, in which case, in particular according to the invention, the inset ii! Since the counter that specifies the horizontal position of the first side SB and the counter that forms the horizontal address signal are also used, it is possible to reduce the number of components such as the counter and peripheral circuits, and reduce the manufacturing time. Cost reduction can be achieved. Also,
Simplicity can also be achieved in services.

Effects of the invention The number of HB parts can be reduced, manufacturing time can be shortened,
It is possible to realize miniaturization, cost reduction, and improved simplicity.

[Brief explanation of drawings]

1, 2, and 4 to 6 are diagrams for explaining this invention, and FIG. 3 is a system diagram of an example of this invention. (16) and (21) are video RAMs, (22) is a counter, (23) and (24) are decoders, and (25) is a signal forming circuit.

Claims (1)

[Claims] Display data stored in the display memory 71 is read out corresponding to horizontal and vertical scanning, and this read display data is supplied to the picture tube and displayed as both images on a single page. A display circuit comprising another display memory, a counter, and a decoder, and in the counter,
Count microtsks (or horizontal period pulses) for each horizontal scan (or vertical scan), and when the counter recurses by a predetermined value, this is detected by the decoder and the counting is continued in the same manner. After the above-mentioned detection output is obtained in the second decoder, the above-mentioned another display memory is activated by the count output of the above-mentioned counter.
Response (a display path that retrieves display data.