JPS5922135A - Data processing circuit - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency of data, by providing a gate period for data access and allowing access to a memory for writing colored data and picture data in the gate period for access even if in a display period. CONSTITUTION:For data transfer to and from a picture memory under CPU control, data is stored in a data register RG3 for writing during writing operation and its address is stored in address RGs 1 and 2 for writing. Data read out of the picture memory is stored in a data RG11 for reading and its address is stored in address RGs 7 and 8 for reading. A colored data gate and a picture data gate are opened during a picture display period, then the access gate is opened. Access gate signal generating means 4 and 5, and 9 and 10 for writing and reading are operated during the access gate period to write and read data and perform automatic increment control over address values during the writing and reading of data by circuits 102 and 104 to shorten data transfer time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention provides a method for writing digital data into memory through processing by a central processing unit (CPU), even though the same address bus is used. The present invention relates to a data processing circuit that allows data to be written while an image corresponding to read data is being reproduced, and that reduces data transfer time.

``Technical Background of the Invention'' An example of a system that writes data into memory through CPU processing and processes the written information is teletext broadcasting1. It is a broadcasting system that multiplexes and transmits digital signals during a period of time and displays image information consisting of characters and graphics on a receiver.

In this teletext broadcast, the image data transmitted during the vertical retrace period is written to the image menu via the CPU, and read out during the screen display period to obtain a reproduced image.

Conventionally, the above-mentioned transmitted image data t is carried out during the so-called non-display period when the image added to the transmission footer on the playback screen is not being played back, and during the image display period, the above image menu is The image data is read out and the image data is reproduced and displayed.

In this case, if the image is a color image, color signal information is transmitted in addition to image data corresponding to the luminance signal h'j' and r.

By the way, one page of the playback screen is usually divided into display sections called blocks and subblocks, and coloring of each page is performed using these sections as units.

Note that the reproduced pixels are divided into, for example, 248 horizontally and 204 vertically, and the subblock serving as the unit area of one coloring is an area of 8 (horizontal) pixels x 12 (vertical) pixels, and is 1°C.

By specifying a color for each subblock, coloring of the corresponding portion in the reproduced image is specified.

In order to display the reproduced image in color in this manner, an image memory that holds image data corresponding to the luminance signal and a color memory that holds the coloring data for the subblock area are provided, and the data in these memories is transferred to the CPU. A reproduced image is obtained by accessing the .

In this case, loading data into memory is performed during a non-display period when image data is not projected. Therefore, when processing image data and colored arcs, it is necessary to determine the non-display period and display period, and to access Therefore, it is necessary to specify the timing of data reading and writing, and the transfer efficiency of data reading and writing inevitably deteriorates.

``Problems in the Background Art'' Namely, when reproducing and displaying transmitted image data such as conventional single-character multiplex broadcasting, in order to transfer data from the CPU to the image memory and color memory, the access must be controlled during non-continuous periods such as the vertical blanking period. This was done using the display period.

Therefore, it is necessary to detect that the CPU is in a non-display period, and a detection means for this is required.
Since data can only be transferred for a short period of time during the non-display period, there is a problem that if the data transfer speed is slow, there will be no luck.

Also used as image memory and color memory I) 11. A,
Using M (dynamic ram), ft fM + and mouth 1
, row address (R, AS), column address (C
The address signal is accessed by dividing the entire address into two parts (AS), but at this time ILAS and CAS control are required to latch the row address and column address, and the CP
It is difficult to directly connect U and I)F'tAM.

Therefore, the address signal is stored in another register, etc., and the I
Generally, it is input to the memory together with the LAS and CAS discrimination control signals.

In this case, the address must be transferred to the address register t7 every time data is written into the memory or data 'CK is taken out from the memory.

As a result, data is only transferred during non-display time, and address transfer efficiency is poor.
1 when accessing data (the conventional problem was that A1 was slow).

To illustrate this conventional problem in the case of teletext broadcasting as an example, as shown in Fig. 1, one display period signal (Fig. 1 8) is detected by CPTJ, and during this period 8 / 5 fsc
A gate signal (FIG. 1C) for colored data every four clocks of a clock signal (FIG. 1B) with a frequency of (fsc color subcarrier frequency).

An image data gate signal (FIG. 1d) having an opposite phase to that of the stiffness is generated.

By kneading, the image memory,
and image data from color memory respectively.

It reads and accesses the colored data and displays it on the screen.

In other words, during the display period (FIG. 1, 8), only data can be read, and neither image data nor colored data is written into the memory.

Data is only written when the CPLI detects a non-display period.

In such data access, data writing is limited to the non-display period, so there is a problem in that it takes time to access the data.

``Purpose of the Invention'' This invention has been made to address the above-mentioned difficulties, and when processing data such as image data of teletext broadcasting, etc., data incorporation is not limited to the non-display period of the image. The purpose of this invention is to make it possible to input data even during the display period, thereby shortening the data transfer time.

Furthermore, this inventive method performs an automatic address increment operation without controlling the switching between upper and lower addresses for each data, thereby shortening the access time for address specification.

The purpose is to improve data transfer efficiency regarding data processing.

"Summary of the Invention" Therefore, in the present invention, a gate period for data access is provided in addition to the coloring data gate period 9 image data gate period in the display interval of the image, and the above access During the gate period, it is possible to access the memory to write coloring data, image data, etc.

With this feature 1, data access other than reading and exporting data is possible between the 1cPU and the memory during the display period, thereby shortening the data access time.

It leaked. When specifying an address, a starting value address is given and the address is automatically incremented each time data is transferred, thereby reducing data access time as much as possible.

Embodiments Hereinafter, embodiments in which the present invention is applied to a teletext broadcasting receiver will be described with reference to the drawings.

In general, the display on both sides of a teletext broadcast is constructed as shown in FIG.

That is, as shown in the figure, in the horizontal direction of the screen, there are X' addresses from 0 to 31 (including buffers), and in the vertical direction, Y addresses from 0 to 215 (including buffers). ga+
J).

The Y address shown here is an address for one line 474, and is an address for a unit pixel in the vertical direction of image data.

Also, 31. Since X8=248 is 9111 times, the coronation display pixel C of the image data is equally divided into 248 H-lines in the horizontal direction and the thickness of one line (/C1t) in the vertical direction.

On the other hand, in the coloring data, the area (subblock) indicated by the hatched area in FIG. 2 is the unit coloring area J1.

Therefore, the Y address of the coloring data is 12 lines with respect to the Y address of the image data.

By the way, when a raw image is constructed in the form shown in the 21st picture, it is composed of approximately 8 bytes of data for one screen.

In this case, 13 bits of t are required as the address.

Here, the 16-bit address of the memory for storing image data and coloring data is time-divisionally performed in 8-bit units.

To specify the address for one screen as described above, 13
bit, but in this embodiment, the row address (R, A
s) When transmitting, transfer 8-bit data by adding 3bj as a dummy to the 5-bit address signal, and use the remaining 8-bit address signal as a column address (CAS).
).

The 5-bit RAS signal described above corresponds to the horizontal X address (0 to 31) of the configuration screen shown in Figure 2, and the 8-bit CAS signal corresponds to the vertical Y address (0 to z15).
corresponds to

The designation of the X address and Y address for these component screens, that is, the transfer of the R, AS, and CAS signals, is performed at the timing shown in FIG. 3. If one colored item is accessed, the colored data gate signal, A major feature of the present invention is that an access gate signal is generated after the image data gate signal is generated, and subsequent access is possible during this period.

The present invention will be explained in detail with reference to FIG. 3 and 4. Now, in the display period (FIG. 3a).

It is assumed that data is read out from memory and the entire image is displayed.

This deficiency, 815fθc (fec: color subcarrier frequency)
of the 3rd clock (3rd [QIb)] with a frequency of
5-bit RAS and 8-bit CA
The X address as No. Si is transferred and the colored data protrudes from the corresponding address (FIG. 53C).

In addition, during the period indicated by Il+, , in FIG.
Extrude tl (Figure 3 d).

In this way, - 6 bits (of 1 byte period (8 clocks of 875 fecs)) during the display period shown in FIG.
(6 clocks) Colored data between tllj1.

Complete reading of image data.

In this invention, during one byte period of data (815fF3c
coloring data (8 clocks worth of 815 fec), 2 bits (2 clocks worth of 815 fec) at the end of reading the bidirectional data, and 4 bits (2 bits worth 8/5) after the start of the next 1 byte period
Provide the access gate signal (Fig. 3e) k during the period of 4 clocks of fec).

During the 2-byte period (815f) between this display u (Figure 3a)
16 clocks of day C), the 4-bit period ff41? <
During this period, in addition to reading the original data, it is possible to read data for image superimposition, etc., or to store data into the memory.

That is, the major feature of this invention is that it can distinguish between non-display, display, 1t, and Q of one image, write data, and read data as necessary.

FIG. 4 shows a data processing circuit according to the present invention that allows access between cp[J and memory regardless of whether it is an image display period or not.

The part indicated by 100 in the figure is [address control g,
The part indicated by (200) is a part related to data access.

In the addressing part indicated by the size fiof:l),
1) is a part that sends an address signal when signing data, and (102) performs control to fully automatically increment the address value.

Similar to this, the address for reading data (~) is (1
Control of the automatic increment of the address value specified in the part 03) is performed in the part (104).

According to the circuit shown in FIG. 4, it is possible to write and read coloring data and image data during the access gate period shown in FIG. 3e.

By (-7), the value of the address to be accessed is automatically incremented, thereby reducing the time required to change the address.

That is, if the value of the data write or the address of the year, name, and neighbor address is ←■, and the value of the address is incremented by +32 by 1,
It has a function of performing a lower address li self ff1 l+increment operation.

In this way, during the access gate period of the circuit C shown in FIG. (3) Disable the self-sleeping increment of the address signal.

For each movement of Towara, the first order [its ty7 times].

(1) Writing data In the circuit shown in Fig. 4, we will explain the transfer of data from the CPU to the memory, that is, the data transfer 1f11.
By executing the T instruction, the start value of the address to which all data should be written is transferred to the writing address registers (1) and (2) via the address bus A.

In this precision, among the 13-bit addresses that make up one screen of 8 bytes, the X address corresponding to the horizontal direction of both sides of the display is transferred to the register (1) as described above. Transfer it to the register with the Y address value (2) corresponding to the vertical direction. 1'], the 8-bit (5-bit) address transferred to register (1) &:, 1: m
2 II+ as shown in +, 17. The 8-bit line address that corresponds to the address (0 to 31) of the drawing surface of the created surface and is transferred to register (2) is the address (0 to 31) in the oak direction.
~125).

The data to be written into the image memory is transferred to the write data register (3) via the upper address bus A1 (address/data bus).

This pulse indicating that the write data is to be transferred is sent to the write data access gate flag circuit (4) and sets the il flag.

When the flag is set in this write data access flag circuit (4), approximately 2.8
/j s every 47) Gj No. A G F (, Acc
eseGate Front) to obtain a write-in data access gate signal to the write-in data access gate generation circuit (5).

Is it transferred to the write data register (3) like this?
In addition, data d, the first arriving AGF signal (Fig. 3 fw
The write data obtained from T41) is stored in the image memory according to the specified address during the write data access period.

The stored data is added by the write data access gate flag circuit (4) and the write data access gate generation circuit (5).

In this way, V is written into the image memory during the access period between CI'U and the memory (1-period shown at T32 in Figure 3).

Note that in Figure 3, the signal not shown in brackets () is a block signal that controls the IP address value, and the signal indicated by II resets the write data access gate generation circuit (5). In the issue.

Here, the above access period (Fig. 3 e) is specified by a signal that applies JJ+ROAG I! ” (No. N (No. 3)
Figure f) and lean signal (;ff's: 11-1
h) will be explained.

*F', At the 1st heat shown in Figure 4, (lamp, 1ilii (indication of 9 1υI l)l).

Hidden 4 (regardless of the distinction between 11, 8 / 5 f8c
During the 16 clocks of the month, one access period (one access Jυ(output l) f m' for every 2 bytes of data is shown in FIG. 3e).

This access period of 1 hour is shown in Figure 4. Applied to the input data access gate signal l#ii (5) fc
A GF (generated in synchronization with No. 4 and reset pulse).

Prev. 1 This Ikikomi Month 1 Data Axis Flag Circuit (
4) and 71 write data access gate generation circuit (
5) 4'Nf can be constructed with a 1) type flip-flop as shown in the 5th section of fzz.

Upper i-bow J] type flip-flop (40), (5f))
The respective 1) terminals of 1) are kept at negative potential, and the 1Li power Q, fc+and
1 (D/1ill flip-flop 5 via path 51
0 clock terminal CK.

D-type flip-flop (40) i(I, ('
The input pulse from PtJ is used as a clock, and its output and the next stage 19-inch flip-flop (
50) and the output of the NAND playback set by the result performed by the entire NAND circuit (41).

On the other hand, the J]jQ11 Noritub frog 5() uses the result obtained by the AND circuit (51) of the output of the previous stage 1) output/refrigeration flop and the A OF signal as a clock pulse. do.

Now, the address of the image memory to which data should be drawn is
C) When the OU 'l' order is transferred from 'IJ to the phase register (1), (2) indicating the 41st flash vC, at this time, the address register (11, (2) of Sat 5 The boat number is decoded by the address decoder, C
I: 'U's write N'l - The pulse corresponding to 1 month is set in the register 1, and the addresses are stored in registers (1) and (2).

The data to be written to this 5-image memory must be transferred to the 4-writing data register (3).

At this time, the input data transfer pulse (Fig. 6a) for fetching data from the address decoder (not shown) to the input data register is sent to terminal 1), [ Sent.

When the write data transfer pulse is applied to the terminal I) in FIG. 5, the output terminal Jd of the D-type clip flap 40:
” ) 1 ” level.

The period of this terminal Q level or "H" level (Figure 6b)
The AGF signal (FIG. 6 0) is added to the AND circuit 51t/1.1. ) (1, lj flip-flop 5
Level 0 of the output terminal Q of 0, TJ l, ' Change shift from I level to II 14 JJ level (η1, 6 d)
).

The level of the 1-11 power of this j) J, j flip-flop 50 is determined by the reset pulse (Fig. f) maintains the ``]I'' level at the reset terminal U of the D-type flip-flop 50.

D5. When a reset pulse is applied to the reset quadrature of the flip-flop 50, its output becomes 111.1 I
+ level to n], rr level ((changes.

As a result, the input access gate signal (the sixth Figure d) All occurs. (still,
This write access gate signal (Fig. 6 (1) is
A shown in Figure 3 θ? Corresponds to number j. ) A, D based on the reset pulse obtained based on the OF signal and signal IP
The pulse width of the write access gate generated by the type flip-flop (50) is Fi 7 (1(1, ase
(/And this access gate for Shishikomi!) Intermediate V
The address is transferred from the C4* address register (], ), (2) to the image memory via the MA bus.

Data is written via the L7 bus (MI).

(2) 2-dimensional extraction of data Next, in one display period, 1KT7'-Y is read and extracted from the CPU other than for the original display. , performs almost the same operation as the write-in operation, but differs from the write-in operation in that one write is made between each write and one address can be read out without any effort.

First, as in the case of the write operation, the address ij OU 'I' of the image memory to be retrieved is
The CPU y2 fi reads the data and transfers it to the read byte address shift register (7) and the read line address shift register (8) via the address bus A Di.

Unlike the case of data staleness, the address is
l, J], and read out the data directly to the oJ meeting [
It becomes 1.

Access gate signal when reading data (Fig. 3 e)
The read access gate flag circuit (9
), B, data access gate generation circuit for protrusion (1
0) is structured 11 in the same way as in the case of data logging shown in FIG.

When a line address transfer pulse for leakage S leakage is applied from the CPU to terminal I (1), the trailing edge of this pulse constitutes the access gate flag circuit (9) for leakage S leakage. The output of the type flip-flop Q is rr
11 rr level.

Data transfer from image memory 1. Extrusion is now permitted.

In this way, the read access gate flag circuit (
9) is set to H'', the above-mentioned A(J, F', it' signals (fPiJ6) are set as in the case of writing.

) is applied to the read access gate generation circuit (10).

This force causes the read access gate generation circuit (
An access gate signal for reading and accessing is generated at the output of 10).

During the access gate period obtained in this way, an address is supplied to the address bus.
11) Data to be read from the image memory is transferred via the data bus.

Then, an IN command from the CPU causes the data to be read in C and PUK i'1 via the AD path.

The IN command in this case corresponds to the read data transfer pulse applied to the terminal R2 in FIG.

In this way, the data is adjusted to the appropriate size for C, I) tJ.
Then, in order to read the next data from both f-parallel memories to the read data register (11), a read data transfer pulse is applied to the -h terminal lmo.
The output of the read access gate flag circuit (9) becomes the JJH, LL level again, making it possible to read the next data and continue reading the data.

(3) Automatic address increment As mentioned above, data is written or read during the access gate period shown in θ in Figure 3, and data transfer efficiency is improved by changing the address for each access. For.

In this embodiment, the address value is automatically incremented.

This increment of the address is performed according to the subdivision of the configuration screen shown in FIG.

As shown in FIG. 2, in this embodiment, pixels are subdivided into 32 bytes in the X address direction, so the compensation for the X address is fixed and the value of the X address (vertical direction) is +1.
When the number is increased by increments, the address corresponding to the vertical direction (Y direction) is changed.

On the other hand, if the Y address is fixed and the value of the X address (byte address) in the horizontal direction is increased by -1, the corresponding address in the horizontal direction will be changed.

That is, to select data to be accessed in the horizontal direction on the configuration screen shown in FIG. 2, it is sufficient to fix the X address and increase the X address by +1.

Talented. To select data in the vertical direction, it is necessary to fix the X address and increase the X address by +1.

Incidentally, since the pixel is divided into 32 in the X direction, increasing the X address by +1 corresponds to increasing the value of the address as a whole by +32.

Following such address value changes, the access 11
The data changes, but the address of the X address (ij5
(r) An 8-bit shift register is used for the wrap-around 1-byte address shift register (]), 'fle, and extra-byte address shift register (7) to be communicated.

For this reason, it takes 9 steps to change the address value of the X address! ,1
:, 8 pulses are required.

1′! II. To change the address value in the X direction, 17
A total of t8 pulse trains are required.

This pulse train is applied to the access gate number (3rd
1 mele) Trailing edge part f issue, Access gate generation circuit for evening recess (511R protrusion 7 access gate generation cow IJlh! Each (10) 'i milli reset count = issue (No. If you hit the mark in figure 3 h), you will definitely get 1 hit.

When the access gate signal cycle shown in FIG. 3 (FIG. 3 e) is reached, the regular access to r9 is completed. χ・1
In order to set the address value of the address of data to be accessed next, the above-mentioned nocil sequence for changing the X address is generated with the arrival of the above-mentioned e reset pulse (h in FIG. 3).

This means data acquisition, data reading, data extraction,
The same is true in the case of 0. K that changes the address value in this way is (1) Detecting the generation of the access gate signal and using the above 8/5 f necessary to change the X address.
Generation of a pulse train of pulses with a frequency of ec.

(2) Generating a pulse (IP) to change the address value.

02 operations are required.

It is the pulse train generating circuit 6 shown in FIG. 4 that performs the stiff operation, and the details 1 of this pulse train generating circuit 6 are shown in FIG. 7, and its timing chart is shown in FIG. Let me explain that.

First, the reset pulse (Fig. 3) used to determine the period of the access gate signal, i, is the original pulse IP generated by an oscillator (not shown) which oscillates at a frequency of +8/5 feC. It is generated from the output by the IP pulse generation (b) path 30 and applied to the terminal (P, ) of the pulse train generation circuit (6).

The IP pulse generating circuit 30 generates a pulse every 16 bits (Fig. 8h) from the first pulse of the 815 fec clock (Fig. 8).

This No. 411 IP is generated by <14 access gate generation circuit (5) + it extraction J11 access gate generation circuit (10) and is connected to terminals (P2), (P, ,
A reset pulse (grs_s_lc)'? that defines the details of the signal interval of the access gate signal applied to the pulse train generating circuit (6) shown in FIG. It is used to generate r4￥.

That is, the input terminal (
31), the access gate 1 word (the RLSI θ) is applied to the terminals (Pz) and (P, ).

d) and the signal 1.1' (Fig. 8b) by the AND circuit (20) (v+ys Fig. f) is applied. +ru.

An 8/5 fsc clock (Fig. 8) is applied to the clock terminal (CK) of the shift register (29) through the terminal (1', )i, and therefore the shift register (29) The terminal (P,) on the output terminal (Q, ) side of the first stage has a half circuit (5) for writing access gate (5) 9Ml: access gate generation circuit for protrusion (10) - reset l) set. Pulse (Fig. 5f)
,F:81')lc)'zall occur.

Access gate by kneading! 1. f1 (Fig. 8d).

e) the trailing edge is determined and the access gate opening is determined;

In this way, the pulse train generation [jl path (6
) id, generates a reset pulse to write and read data access I! In addition to determining J1++-1fa, it has a function of generating a pulse train kQ for automatically incrementing the address for the next data to be accessed.

This pulse train is applied to the write access gate (fR
8 d), corresponding to the read access gate (FIG. 8 θ) (FIG. 8 d), it is necessary to generate it at the (8th] sila, h) I.

First, let's discuss the generation of a pulse train for changing an address when reading one image data.

The read access gate (FIG. 8 θ) is generated, and the output of the AND circuit (20) (FIG. 8 f) & j, 1
1+ is added to the data terminal σ)) of the ) type flip-flop (21).

The tally terminal (C) of this D-type flip-flop (21)
Since the phase of the fsc clock (Fig. 8) is inverted [7] is added to the output terminal (C), the pulse 1 is output to the output terminal (C)l. ．． l).

A signal delayed by half a clock of all 815fθC is inputted.

Part 1. Lever signal (81'<l i ) ItU2,
6°C extension access game added to terminal (P2) (No. 8 (Tate 8 figure θ) and AND circuit 22 perform logic-
output (jp,
8 l'>'l j ) is an R, S flip-flop (
23) used as set number 13.

The shift register (29) has an 8-bit configuration, and its final stage output (Q8) is connected to one input terminal of the AND circuit (28), and the other input terminal of the AND circuit (28) is connected to the R /5 fec clock is applied.

Therefore, the output of the AND circuit (28) becomes as shown in FIG.
23) is used as a reset signal.

Therefore, the RS flip-flop (23) is as shown in FIG.
It is set by the output signal of the AND circuit (22) shown in FIG. 8, and reset by the output signal of the AND circuit (28) shown in FIG. 8k.

By kneading, a gate signal as shown in FIG. 81 is obtained at the output of the RS flip-flop (23).

This start signal (Fig. 8 1) is applied to one input terminal of the AND circuit (24), and the above-mentioned 8/
A clock of 5 fec is added.

As a result, the output of the AND circuit (24) (terminal P,)
8 / immediately after the read access gate period.
Generates 8 clocks of 5 fee clocks.

The pulse train obtained at this terminal P is applied to a 1-bit full adder (12) and a clock switching circuit (14) shown in FIG.

In addition, the 1-bit full adder (12) has a signal IP
is added, and the augend data to be added is controlled by the augend data switching circuit (14).

That is, in the configuration diagram shown in FIG. 2, the address value is +32.
When changing the address in the Y direction by incrementing, it is necessary to change the value of the 8-bit reading line address shift register (8).

Now, when the pulse train shown in Figure 8g is obtained at the terminal (P6) of the pulse train generation circuit (6), the clock switching circuit (13) controls to add this 'h to the readout line address shift register (8). Control.

The pulse train (8th
When the line address register (8) for reading is added, the value of the read line address register (8) increases by +1.0 This increase is due to the action of the augend data switching circuit (14), so that only the upper address increases, and the address of the upper address Although the value is increased by 1.

Overall, the address value is incremented by +32.

When the pulse train is added to the read line address shift register (8) in this way, +1 is added to the previous Y address by the 1-bit full adder (12), and the address value of the read line address shift register (8) is is set to the address value of the data to be accessed first.

In this way, address values of data to be newly accessed are sequentially set in the vertical direction.

Next, we will discuss the case where the address in the X direction is changed. In this case, the above-mentioned nozzle string (h in Figure 8) is changed to the read byte address shift register ( 7) is applied only.

Therefore, the read byte address shift register (
The output of 7) increases by +1.

The address value incremented by +1 by kneading is set to the read byte address shift register (7) to 0. The address in the X direction is incremented by kneading.

In this way, the address value can be changed in both the X and Y directions without going through the %Cl) U, and data transfer efficiency is improved.

As mentioned above, the increment of the address at the time of reading is described above, but the address can be changed in the same way when writing data. This is done by means of a pulse train (Fig. 8h) obtained at terminal (P7) of circuit (6).

That is, a full adder (15), a clock switching circuit (16),
The addend data switching circuit (17) increments the addresses in the X and Y directions as in the case of reading, and sets the address of the data to be written next.

The address thus changed is transferred to the memory via the memory address bus, and the data is accessed via the memory's data bus.

In addition, the upper assignment ζ address can be changed by →-1 or +32
in the X direction.

Alternatively, the address value is changed sequentially in the Y direction, but whether or not the address value is incremented in the chair mode is controlled by the assistance mode registers (18) and (19).

"Effects of the Invention" As described above, according to the present invention, even during the so-called display period when data to be displayed is read from the image memory,
Allows access for data writing or reading data for purposes other than direct display. ) Due to stiffness, data write access is no longer limited to the non-display period, and data access efficiency is improved.

Also, in order to access the data, change the address to address 4 minutes instead of changing it via CP [1].
Since the address is automatically incremented when only the leading value address is obtained, the present invention provides a data processing circuit that can significantly reduce data processing time.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the operation of a conventional data processing circuit, FIG. 2 is an explanatory diagram for explaining the entire configuration of a display screen displayed by the data processing circuit, and FIG. 4 is a circuit diagram showing an embodiment of a data processing circuit according to the present invention,
5 and 7 are circuit diagrams showing details of the circuit shown in FIG. 4. 6 and 8 are waveform diagrams showing timing relationships for explaining the operation of the data processing circuit according to the present invention. 3......Write data register 11.
...Read data register 4.5...
...Writing access gate signal generation means 9
．． 10...Access gate signal generation means for reading 5.6.10...- Data access gate signal generation means procedure amendment (method) Commissioner of the Japan Patent Office Kazuo Wakasugi Indication of the Tonoori Case Patent Application No. 180245/1983 2 Name of the Invention Data Processing Circuit 3 Relationship to the Amendment Case Patent Applicant (BO7) Tokyo Shibaura Electric Co., Ltd. 4 Agent Address: 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo 100 October 26, 1982 (Shipping date) 1 on page 36, line 10 of the specification attached to this application...Explanatory diagram;
What does Figure 4 say? ]--... Figure 3 is a waveform diagram for explaining the timing of the data processing operation by the data processing circuit according to the present invention, and Figure 4 is corrected as ]. that's all

Claims (1)

[Claims] An image memory that stores data to be displayed via a CPU, and a display device that decodes and displays the image data in the image memory. a write data register that stores data to be written into the image memory; and a write address register that stores an address of the write data. a read data register for storing data read from the image memory; a read address register for Ifa the address of the read data; When transferring data to be displayed from the image memory to the display encoder during the first and second j-ta bA: output gate periods, after the first readout gate signal, the C
Either the transfer of data from the PU to the data register for writing, the transfer of an address to the address register for continuous output, or the transfer of data in the notator register for reading to the CPU. The first data read gate signal and the @2
and a means for generating a data access signal for performing sorter control on the write register or the read register during a data read signal period of the image memory and the display encoder. A data processing circuit characterized in that data control is performed on the write register or the read data register even during a display period.