JPS6464236A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6464236A JPS6464236A JP62220742A JP22074287A JPS6464236A JP S6464236 A JPS6464236 A JP S6464236A JP 62220742 A JP62220742 A JP 62220742A JP 22074287 A JP22074287 A JP 22074287A JP S6464236 A JPS6464236 A JP S6464236A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- implanting
- tin
- film
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To form a wiring, the resistance value of which hardly changes and which has fine size, by selectively implanting N ions into a Ti film in high concentration, respectively shaping TiN to an implanting layer and a Ti silicide to a region except the implanting layer through annealing and selectively removing only TiN through a wet etching method. CONSTITUTION:Double layer films consisting of a polysilicon film 3 and a Ti film 4 are formed through a process in which a gate for a MOS transistor element is shaped, and nitrogen ions are implanted, using a photo-resist film 5 as a shielding mask. The photo-resist 5 is gotten rid of, and TiN 8 is formed to a nitrogen ion implanting layer and a Ti silicide layer 9 to a non-implanting layer respectively through annealing in an inert gas such as Ar. The TiN layer 8 is melted and the Ti silicide layer 9 is left by dipping the whole into the mixed liquid of H2O2+NH4OH+H2O. The Ti silicide layer is stabilized through annealing at 850-900 deg.C. A polysilicon film under the residual implanting layer is removed by using a dry etching method, thus shaping a wiring pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62220742A JPH0734441B2 (en) | 1987-09-03 | 1987-09-03 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62220742A JPH0734441B2 (en) | 1987-09-03 | 1987-09-03 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6464236A true JPS6464236A (en) | 1989-03-10 |
JPH0734441B2 JPH0734441B2 (en) | 1995-04-12 |
Family
ID=16755817
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62220742A Expired - Lifetime JPH0734441B2 (en) | 1987-09-03 | 1987-09-03 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0734441B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5987374A (en) * | 1996-07-08 | 1999-11-16 | Toyota Jidosha Kabushiki Kaisha | Vehicle traveling guidance system |
-
1987
- 1987-09-03 JP JP62220742A patent/JPH0734441B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5987374A (en) * | 1996-07-08 | 1999-11-16 | Toyota Jidosha Kabushiki Kaisha | Vehicle traveling guidance system |
Also Published As
Publication number | Publication date |
---|---|
JPH0734441B2 (en) | 1995-04-12 |
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