JPS6462745A - Address converting system - Google Patents

Address converting system

Info

Publication number
JPS6462745A
JPS6462745A JP62220619A JP22061987A JPS6462745A JP S6462745 A JPS6462745 A JP S6462745A JP 62220619 A JP62220619 A JP 62220619A JP 22061987 A JP22061987 A JP 22061987A JP S6462745 A JPS6462745 A JP S6462745A
Authority
JP
Japan
Prior art keywords
address
page
conversion buffer
address conversion
registered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62220619A
Other languages
Japanese (ja)
Inventor
Yuzo Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62220619A priority Critical patent/JPS6462745A/en
Publication of JPS6462745A publication Critical patent/JPS6462745A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To decrease the rate at which a desired page is not registered in an address conversion buffer, by registering plural continuous pages in one entry of the address conversion buffer. CONSTITUTION:In one entry of an address conversion buffer, a 2-page portion is contained and the least significant bit 102 of a page number P is used for selecting a page '0' and a page '1' by a selecting circuit 7. At the time of indexing the address conversion buffer 2, the contents of the corresponding entry are read out by a set address 101, and a key part 11 and a comparison address of a logical address register 1 are compared by a comparator 3. When both of them coincide, and also, an effective bit 10 is ON, information corresponding to an address of the logical address register is registered in the address conversion buffer 2. In this case, by a real page number 104 from a selecting circuit 7 and a line address 105 from the logical address register 1, a desired real address is set to a real address register 6. In such a way, a rate at which a desired page is not registered in the address conversion buffer can be decreased.
JP62220619A 1987-09-02 1987-09-02 Address converting system Pending JPS6462745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62220619A JPS6462745A (en) 1987-09-02 1987-09-02 Address converting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62220619A JPS6462745A (en) 1987-09-02 1987-09-02 Address converting system

Publications (1)

Publication Number Publication Date
JPS6462745A true JPS6462745A (en) 1989-03-09

Family

ID=16753810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62220619A Pending JPS6462745A (en) 1987-09-02 1987-09-02 Address converting system

Country Status (1)

Country Link
JP (1) JPS6462745A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006525607A (en) * 2003-04-30 2006-11-09 シリコン・グラフィックス・インコーポレイテッド System and method for performing address translation in a computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006525607A (en) * 2003-04-30 2006-11-09 シリコン・グラフィックス・インコーポレイテッド System and method for performing address translation in a computer system

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