JPS6460895A - Read only memory - Google Patents

Read only memory

Info

Publication number
JPS6460895A
JPS6460895A JP21821987A JP21821987A JPS6460895A JP S6460895 A JPS6460895 A JP S6460895A JP 21821987 A JP21821987 A JP 21821987A JP 21821987 A JP21821987 A JP 21821987A JP S6460895 A JPS6460895 A JP S6460895A
Authority
JP
Japan
Prior art keywords
address
address latch
memory
content
address data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21821987A
Other languages
Japanese (ja)
Inventor
Makoto Mifuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21821987A priority Critical patent/JPS6460895A/en
Publication of JPS6460895A publication Critical patent/JPS6460895A/en
Pending legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable the content of address data in an address latch to be rewritten even in making access to a memory, by providing the address latch which latches the address data corresponding to an arbitrary one channel selected out of plural channels. CONSTITUTION:A prescribed control signal is outputted from a controller 6, and is sent to a selector 3, and the content of the address latch 1 or 2 of a selected channel is inputted from the selector 3 to the address latch 4. Meanwhile, the prescribed control signal is also sent to the address latch 4, and the content of the address data inputted from the selector 3 via the control signal is latched at the address latch 4 as the address data to make access to the memory 5. In such a way, at a time after the address data to make access to the memory 5 is latched at the address latch 4, it is possible to rewrite the content of the address data of the address latch 1 or 2 freely.
JP21821987A 1987-08-31 1987-08-31 Read only memory Pending JPS6460895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21821987A JPS6460895A (en) 1987-08-31 1987-08-31 Read only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21821987A JPS6460895A (en) 1987-08-31 1987-08-31 Read only memory

Publications (1)

Publication Number Publication Date
JPS6460895A true JPS6460895A (en) 1989-03-07

Family

ID=16716480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21821987A Pending JPS6460895A (en) 1987-08-31 1987-08-31 Read only memory

Country Status (1)

Country Link
JP (1) JPS6460895A (en)

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