JPS6459560A - Bus controller - Google Patents

Abstract

PURPOSE:To easily perform multiple address communication to arbitrary processors, by storing only bus controllers whose multiple address communication display coincide with each other in a communication origin processor display holding means, and deciding the processor of a communication origin from which the multiple address communication is issued. CONSTITUTION:Comparison between communication destination processor display data 210 and multiple address communication display data 211 is performed at a processor display comparator 203, and when coincidence is obtained, a processor communication request 212 is supplied to a communication origin processor display register 204. To the communication origin processor display register 204, processor origin processor display data transmitted from the bus controller 102 of the communication origin is inputted via the data signal line of a common bus. When the communication origin processor display data is stored in the communication processor display register 204 by the processor communication request 212, an interruption signal 115 is outputted to a processor 103. Since the processor 103 reads out the communication origin processor display data stored in the communication origin processor display register 204 in the bus controller 104 by the interruption signal 115 from the bus controller 104, it is possible to perform the multiple address communication easily.