JPS6444558A - Memory access control system - Google Patents
Memory access control systemInfo
- Publication number
- JPS6444558A JPS6444558A JP62199975A JP19997587A JPS6444558A JP S6444558 A JPS6444558 A JP S6444558A JP 62199975 A JP62199975 A JP 62199975A JP 19997587 A JP19997587 A JP 19997587A JP S6444558 A JPS6444558 A JP S6444558A
- Authority
- JP
- Japan
- Prior art keywords
- request
- port
- mab
- mcu
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Memory System (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To speed up abnormality processing by deciding whether an address in a data buffer (MAB) for storing read data coincides with a MAB for storing write data or not when a write request is abnormally ended by some reason before generating a read request, and when both the addresses coincide with each other, information abnormal end without waiting the read request. CONSTITUTION:When a port receives a request, the port status goes to a priority order waiting state. A port controller (PC) selects a port with the highest priority out of the priority waiting ports and outputs a request to a memory control unit (MCU). Data returned to the MCU by accessing a main memory (MSU) from the MCU are returned to the port controller (PC). The port controller (PC) decides whether the executed processing is normal or abnormal independently of the coincidence/discrepancy of the MAB address. At the time of abnormal end, the port status is abnormally ended and an abnormal end code is sent by another request.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62199975A JP2594567B2 (en) | 1987-08-12 | 1987-08-12 | Memory access control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62199975A JP2594567B2 (en) | 1987-08-12 | 1987-08-12 | Memory access control device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6444558A true JPS6444558A (en) | 1989-02-16 |
JP2594567B2 JP2594567B2 (en) | 1997-03-26 |
Family
ID=16416699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62199975A Expired - Fee Related JP2594567B2 (en) | 1987-08-12 | 1987-08-12 | Memory access control device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2594567B2 (en) |
-
1987
- 1987-08-12 JP JP62199975A patent/JP2594567B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2594567B2 (en) | 1997-03-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0288649B1 (en) | Memory control subsystem | |
US4674033A (en) | Multiprocessor system having a shared memory for enhanced interprocessor communication | |
US4698746A (en) | Multiprocessor communication method and apparatus | |
US4754398A (en) | System for multiprocessor communication using local and common semaphore and information registers | |
US4975838A (en) | Duplex data processing system with programmable bus configuration | |
KR970029014A (en) | Data Processing System and Method | |
AU5394290A (en) | Memory configuration for use with means for interfacing a system control unit for a multi-processor system with the system main memory | |
US4691280A (en) | High performance multi-processor system | |
JPH01269142A (en) | Buffer memory control system | |
EP0223607A2 (en) | Vector processing system | |
US4493030A (en) | Plural data processor groups controlling a telecommunications exchange | |
JPS6242306B2 (en) | ||
JPS6444558A (en) | Memory access control system | |
EP0289771B1 (en) | Dual microprocessor control system | |
JPH0140432B2 (en) | ||
JPS62135038A (en) | Data communications system for slave processor | |
GB2099619A (en) | Data processing arrangements | |
SU1541623A1 (en) | Device for interfacing computer with peripheral device | |
KR910005379B1 (en) | Memory board used for control function distribution in main storage system of data processing system | |
KR960003650B1 (en) | Input/output processor for improving computer system performance | |
JPS6217879Y2 (en) | ||
JPH01296352A (en) | Duplex processor | |
JPS6373458A (en) | Shared memory access device | |
JPS63245745A (en) | Buffer storage controller | |
JPH04160446A (en) | Multi-port memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |