JPS6444558A - Memory access control system - Google Patents

Memory access control system

Info

Publication number
JPS6444558A
JPS6444558A JP62199975A JP19997587A JPS6444558A JP S6444558 A JPS6444558 A JP S6444558A JP 62199975 A JP62199975 A JP 62199975A JP 19997587 A JP19997587 A JP 19997587A JP S6444558 A JPS6444558 A JP S6444558A
Authority
JP
Japan
Prior art keywords
request
port
mab
mcu
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62199975A
Other languages
Japanese (ja)
Other versions
JP2594567B2 (en
Inventor
Hiroyuki Egawa
Makoto Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62199975A priority Critical patent/JP2594567B2/en
Publication of JPS6444558A publication Critical patent/JPS6444558A/en
Application granted granted Critical
Publication of JP2594567B2 publication Critical patent/JP2594567B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To speed up abnormality processing by deciding whether an address in a data buffer (MAB) for storing read data coincides with a MAB for storing write data or not when a write request is abnormally ended by some reason before generating a read request, and when both the addresses coincide with each other, information abnormal end without waiting the read request. CONSTITUTION:When a port receives a request, the port status goes to a priority order waiting state. A port controller (PC) selects a port with the highest priority out of the priority waiting ports and outputs a request to a memory control unit (MCU). Data returned to the MCU by accessing a main memory (MSU) from the MCU are returned to the port controller (PC). The port controller (PC) decides whether the executed processing is normal or abnormal independently of the coincidence/discrepancy of the MAB address. At the time of abnormal end, the port status is abnormally ended and an abnormal end code is sent by another request.
JP62199975A 1987-08-12 1987-08-12 Memory access control device Expired - Fee Related JP2594567B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62199975A JP2594567B2 (en) 1987-08-12 1987-08-12 Memory access control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62199975A JP2594567B2 (en) 1987-08-12 1987-08-12 Memory access control device

Publications (2)

Publication Number Publication Date
JPS6444558A true JPS6444558A (en) 1989-02-16
JP2594567B2 JP2594567B2 (en) 1997-03-26

Family

ID=16416699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62199975A Expired - Fee Related JP2594567B2 (en) 1987-08-12 1987-08-12 Memory access control device

Country Status (1)

Country Link
JP (1) JP2594567B2 (en)

Also Published As

Publication number Publication date
JP2594567B2 (en) 1997-03-26

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees