JPS6459089A - Lsi with test circuit - Google Patents

Lsi with test circuit

Info

Publication number
JPS6459089A
JPS6459089A JP62215609A JP21560987A JPS6459089A JP S6459089 A JPS6459089 A JP S6459089A JP 62215609 A JP62215609 A JP 62215609A JP 21560987 A JP21560987 A JP 21560987A JP S6459089 A JPS6459089 A JP S6459089A
Authority
JP
Japan
Prior art keywords
signal
lsi
test
circuits
function block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62215609A
Other languages
Japanese (ja)
Inventor
Toshiaki Machida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62215609A priority Critical patent/JPS6459089A/en
Publication of JPS6459089A publication Critical patent/JPS6459089A/en
Pending legal-status Critical Current

Links

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To test a LSI in a short time by putting plural equal-function block circuits that the LSI has in parallel operation and thus testing the LSI. CONSTITUTION:A test control circuit 5 receives a test signal S3 and generates a test control signal for setting N equal-function block circuits 5-1, 5-2,...5-N a test state wherein simultaneous parallel operation is performed. An output circuit 7 sends out a signal from an internal bus 6 as an output signal S4. A comparing circuit 8 receives respective outputs when the circuits 5-1, 5-2,-5-N perform processing operation by receiving the same pattern and compares them with the signal from the internal bus 6, thereby outputting a comparison signal S5 as the comparison result indicating whether or not they are coincident. The signals S4 and S5 are observed to know whether the circuits 5-1, 5-2,...5-N7 are normal or abnormal.
JP62215609A 1987-08-28 1987-08-28 Lsi with test circuit Pending JPS6459089A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62215609A JPS6459089A (en) 1987-08-28 1987-08-28 Lsi with test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62215609A JPS6459089A (en) 1987-08-28 1987-08-28 Lsi with test circuit

Publications (1)

Publication Number Publication Date
JPS6459089A true JPS6459089A (en) 1989-03-06

Family

ID=16675256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62215609A Pending JPS6459089A (en) 1987-08-28 1987-08-28 Lsi with test circuit

Country Status (1)

Country Link
JP (1) JPS6459089A (en)

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