JPS645887Y2 - - Google Patents

Info

Publication number
JPS645887Y2
JPS645887Y2 JP1982085369U JP8536982U JPS645887Y2 JP S645887 Y2 JPS645887 Y2 JP S645887Y2 JP 1982085369 U JP1982085369 U JP 1982085369U JP 8536982 U JP8536982 U JP 8536982U JP S645887 Y2 JPS645887 Y2 JP S645887Y2
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor chip
present
electrode metal
built
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982085369U
Other languages
English (en)
Japanese (ja)
Other versions
JPS58191638U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1982085369U priority Critical patent/JPS58191638U/ja
Publication of JPS58191638U publication Critical patent/JPS58191638U/ja
Application granted granted Critical
Publication of JPS645887Y2 publication Critical patent/JPS645887Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
JP1982085369U 1982-06-10 1982-06-10 半導体ペレツト Granted JPS58191638U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982085369U JPS58191638U (ja) 1982-06-10 1982-06-10 半導体ペレツト

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982085369U JPS58191638U (ja) 1982-06-10 1982-06-10 半導体ペレツト

Publications (2)

Publication Number Publication Date
JPS58191638U JPS58191638U (ja) 1983-12-20
JPS645887Y2 true JPS645887Y2 (enrdf_load_stackoverflow) 1989-02-14

Family

ID=30094246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982085369U Granted JPS58191638U (ja) 1982-06-10 1982-06-10 半導体ペレツト

Country Status (1)

Country Link
JP (1) JPS58191638U (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS58191638U (ja) 1983-12-20

Similar Documents

Publication Publication Date Title
US7129116B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2522524B2 (ja) 半導体装置の製造方法
US7274088B2 (en) Flip-chip semiconductor package with lead frame as chip carrier and fabrication method thereof
EP1500130A1 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP2653179B2 (ja) 集積回路装置用バンプ電極の製造方法
JP2001015668A (ja) 樹脂封止型半導体パッケージ
JP2000243887A (ja) 半導体装置とその製造方法
JP2007201324A (ja) 電子装置の実装構造および電子部品の実装方法
US6153921A (en) Diode device
JPS645887Y2 (enrdf_load_stackoverflow)
US6677662B1 (en) Clamp and heat block assembly for wire bonding a semiconductor package assembly
TW419756B (en) Process for producing BGA type semiconductor device, TAB tape for BGA type semiconductor device, and BGA type semiconductor device
JPS63124434A (ja) 半導体装置の製造方法
JP2000243880A (ja) 半導体装置とその製造方法
JPH08148623A (ja) 半導体装置
USRE38043E1 (en) Lead frame
JPH0427148A (ja) 半導体装置用リードフレーム
JP2013012567A (ja) 半導体装置
KR950006837Y1 (ko) 아웃리드 표면 노출형 반도체 패키지
JPS61128548A (ja) 半導体装置
JPS624364A (ja) シヨツトキ−バリアダイオ−ド
JPH05206216A (ja) テープキャリア、半導体装置実装体及び実装方法
JPS5844593Y2 (ja) ビ−ム・リ−ド型半導体装置
JPS6190452A (ja) 半導体装置用リ−ドフレ−ム