JPS6457494A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6457494A JPS6457494A JP62215915A JP21591587A JPS6457494A JP S6457494 A JPS6457494 A JP S6457494A JP 62215915 A JP62215915 A JP 62215915A JP 21591587 A JP21591587 A JP 21591587A JP S6457494 A JPS6457494 A JP S6457494A
- Authority
- JP
- Japan
- Prior art keywords
- bit lines
- inverse
- adjacent
- capacity coupling
- coupling noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62215915A JPH07105134B2 (ja) | 1987-08-28 | 1987-08-28 | 半導体記憶装置 |
US07/236,361 US4922459A (en) | 1987-08-28 | 1988-08-25 | Dynamic semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62215915A JPH07105134B2 (ja) | 1987-08-28 | 1987-08-28 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6457494A true JPS6457494A (en) | 1989-03-03 |
JPH07105134B2 JPH07105134B2 (ja) | 1995-11-13 |
Family
ID=16680359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62215915A Expired - Fee Related JPH07105134B2 (ja) | 1987-08-28 | 1987-08-28 | 半導体記憶装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US4922459A (ja) |
JP (1) | JPH07105134B2 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0362393A (ja) * | 1989-07-31 | 1991-03-18 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPH03171492A (ja) * | 1989-11-30 | 1991-07-24 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPH04168687A (ja) * | 1990-10-31 | 1992-06-16 | Samsung Electron Co Ltd | 半導体メモリ装置 |
JPH04247388A (ja) * | 1991-02-01 | 1992-09-03 | Mitsubishi Electric Corp | 半導体装置 |
JP2011187804A (ja) * | 2010-03-10 | 2011-09-22 | Toppan Printing Co Ltd | 極端紫外線露光用マスクの製造方法 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5214601A (en) * | 1986-12-11 | 1993-05-25 | Mitsubishi Denki Kabushiki Kaisha | Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers |
US4992981A (en) * | 1987-06-05 | 1991-02-12 | International Business Machines Corporation | Double-ended memory cell array using interleaved bit lines and method of fabrication therefore |
JP3005223B2 (ja) * | 1988-06-27 | 2000-01-31 | 日本電気アイシーマイコンシステム株式会社 | 半導体記憶装置 |
DE3937068C2 (de) * | 1988-11-07 | 1994-10-06 | Toshiba Kawasaki Kk | Dynamische Halbleiterspeicheranordnung |
JP2650377B2 (ja) * | 1988-12-13 | 1997-09-03 | 富士通株式会社 | 半導体集積回路 |
JPH0775116B2 (ja) * | 1988-12-20 | 1995-08-09 | 三菱電機株式会社 | 半導体記憶装置 |
JPH03171662A (ja) * | 1989-11-29 | 1991-07-25 | Sharp Corp | 信号線システム |
FR2668640A1 (fr) * | 1990-10-30 | 1992-04-30 | Samsung Electronics Co Ltd | Memoire a semi-conducteurs possedant des lignes de bit et des lignes de mot qui se croisent. |
JPH04271086A (ja) * | 1991-02-27 | 1992-09-28 | Nec Corp | 半導体集積回路 |
US5287322A (en) * | 1991-07-17 | 1994-02-15 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit dual-port memory device having reduced capacitance |
US5311477A (en) * | 1991-07-17 | 1994-05-10 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit memory device having flash clear |
US5440506A (en) * | 1992-08-14 | 1995-08-08 | Harris Corporation | Semiconductor ROM device and method |
JP3440335B2 (ja) * | 1993-08-18 | 2003-08-25 | 日本テキサス・インスツルメンツ株式会社 | 半導体メモリ装置 |
US5745420A (en) * | 1995-07-31 | 1998-04-28 | Sgs-Thomson Microelectronics, Inc. | Integrated memory circuit with sequenced bitlines for stress test |
KR100210846B1 (ko) * | 1996-06-07 | 1999-07-15 | 구본준 | 낸드셀 어레이 |
KR100278656B1 (ko) * | 1998-05-12 | 2001-02-01 | 윤종용 | 트위스트된비트라인구조를갖는반도체메모리장치 |
US6111773A (en) * | 1998-08-28 | 2000-08-29 | Micron Technology, Inc. | Memory circuit having improved sense-amplifier block and method for forming same |
US6209055B1 (en) * | 1998-10-29 | 2001-03-27 | International Business Machines Corporation | Method and apparatus for reducing noise induced among conductive lines |
US6292383B1 (en) | 2000-04-27 | 2001-09-18 | Stmicroelectronics, Inc. | Redundant memory cell for dynamic random access memories having twisted bit line architectures |
US6304479B1 (en) * | 2000-06-23 | 2001-10-16 | Infineon Technologies North America Corp. | Shielded bit line architecture for memory arrays |
KR100380387B1 (ko) * | 2001-02-08 | 2003-04-11 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 신호 라인 배치 방법 |
JP2005197607A (ja) * | 2004-01-09 | 2005-07-21 | Toshiba Corp | 半導体集積回路装置 |
US20060092749A1 (en) * | 2004-10-29 | 2006-05-04 | Integrated Device Technology, Inc. | Bitline layout in a dual port memory array |
JP4914034B2 (ja) * | 2005-06-28 | 2012-04-11 | セイコーエプソン株式会社 | 半導体集積回路 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60254489A (ja) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | 半導体記憶装置 |
JPS6251096A (ja) * | 1985-08-28 | 1987-03-05 | Nec Corp | 半導体記憶装置 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3942164A (en) * | 1975-01-30 | 1976-03-02 | Semi, Inc. | Sense line coupling reduction system |
-
1987
- 1987-08-28 JP JP62215915A patent/JPH07105134B2/ja not_active Expired - Fee Related
-
1988
- 1988-08-25 US US07/236,361 patent/US4922459A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60254489A (ja) * | 1984-05-31 | 1985-12-16 | Fujitsu Ltd | 半導体記憶装置 |
JPS6251096A (ja) * | 1985-08-28 | 1987-03-05 | Nec Corp | 半導体記憶装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0362393A (ja) * | 1989-07-31 | 1991-03-18 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPH03171492A (ja) * | 1989-11-30 | 1991-07-24 | Toshiba Corp | ダイナミック型半導体記憶装置 |
JPH04168687A (ja) * | 1990-10-31 | 1992-06-16 | Samsung Electron Co Ltd | 半導体メモリ装置 |
JPH04247388A (ja) * | 1991-02-01 | 1992-09-03 | Mitsubishi Electric Corp | 半導体装置 |
JP2011187804A (ja) * | 2010-03-10 | 2011-09-22 | Toppan Printing Co Ltd | 極端紫外線露光用マスクの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JPH07105134B2 (ja) | 1995-11-13 |
US4922459A (en) | 1990-05-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |