JPS6455485U

JPS6455485U -

Info

Publication number: JPS6455485U
Application number: JP15116687U
Authority: JP
Priority date: 1987-09-30
Filing date: 1987-09-30
Publication date: 1989-04-05
Also published as: JPH0441353Y2

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例に係るアナログ時計
の修正回路を示す図、第２図はタイムチヤートで
ある。２……基準信号発生器、８……第１の分周回路
、１０……第２の分周回路、２２……順方向修正
スイツチ、２４……逆方向修正スイツチ、２６…
…信号切換回路、３４……修正モード回路、４４
……シフトレジスタ、８４……駆動回路、１１８
〜１２４……コイル、１２６……駆動切換回路、
１４４……プリセツト回路、１４８……ゲート制
御回路、１５８……修正モード延長回路。 FIG. 1 is a diagram showing a correction circuit for an analog clock according to an embodiment of the present invention, and FIG. 2 is a time chart. 2... Reference signal generator, 8... First frequency dividing circuit, 10... Second frequency dividing circuit, 22... Forward correction switch, 24... Reverse correction switch, 26...
...Signal switching circuit, 34...Correction mode circuit, 44
...Shift register, 84...Drive circuit, 118
~124...Coil, 126...Drive switching circuit,
144...Preset circuit, 148...Gate control circuit, 158...Modification mode extension circuit.

Claims

[Claims for Utility Model Registration] A reference signal generator that generates a reference signal; a first frequency dividing circuit that divides the frequency of the reference signal from the reference signal generator and outputs a correction fast-forward pulse signal; a second frequency divider circuit that further divides the frequency of the signal from the first frequency divider circuit and outputs a normal drive pulse; a forward correction switch; a reverse correction switch; and the first and second frequency dividers. a pulse signal switching circuit that inputs a correction fast-forward pulse signal and a normal drive pulse signal from the circuit and switches and outputs either of the two signals; and operation of either the forward direction correction switch or the reverse direction correction switch. a correction mode circuit that outputs a correction mode signal from time to time until the first pulse is generated from the pulse signal switching circuit after the end of the operation; A shift register that can shift the generation of an output signal in a certain direction and reverse the direction of the shift, a drive circuit that amplifies the output signal from the shift register, and a polyphase motor connected to the drive circuit. An analog clock circuit comprising: a first gate group that receives signals from each output terminal of the shift register and outputs a signal from the shift register when a correction mode signal is generated from the correction mode circuit; The signals from the first gate group are respectively inputted, and the signals from the output terminals adjacent to the signals from the output terminal of the shift register to which the first gate group is input are respectively inputted, and the signals are inputted to the drive circuit. a drive switching circuit comprising a second group of gates to which a signal is applied; and a preset circuit that presets frequency division ratio data of 1/2 in the second frequency dividing circuit in response to stoppage of the correction mode signal of the correction mode circuit. a pulse from the pulse signal switching circuit only when the correction mode signal from the correction mode circuit and the operating signals of the forward correction switch and the reverse correction switch are occurring together or not together; a gate control circuit that supplies signals to the shift register; and a gate control circuit that counts the number of pulse signals applied to the shift register from the end of the reverse direction switch operation, and supplies signals from the correction mode circuit until the count value reaches a set value. A correction mode extension circuit for maintaining generation of a correction mode signal; and a correction circuit for an analog clock.