JPH0267296U - - Google Patents
Info
- Publication number
- JPH0267296U JPH0267296U JP14623388U JP14623388U JPH0267296U JP H0267296 U JPH0267296 U JP H0267296U JP 14623388 U JP14623388 U JP 14623388U JP 14623388 U JP14623388 U JP 14623388U JP H0267296 U JPH0267296 U JP H0267296U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- correction
- pulse signal
- outputs
- generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electromechanical Clocks (AREA)
Description
第１図は本考案の一実施例に係るアナログ時計
の修正回路を示す回路図。第２図は、その動作を
示すタイムチヤート図。
２……基準信号発生器、８……分周回路、１８
……切換回路、２０……順方向修正スイツチ、２
２……逆方向修正スイツチ、４４……補正回路、
６２……輪列、６４……指針、６６……多相モー
タ、７２……補正回路。
FIG. 1 is a circuit diagram showing a correction circuit for an analog clock according to an embodiment of the present invention. FIG. 2 is a time chart showing the operation. 2... Reference signal generator, 8... Frequency dividing circuit, 18
...Switching circuit, 20...Forward correction switch, 2
2... Reverse direction correction switch, 44... Correction circuit,
62...wheel train, 64...pointer, 66...polyphase motor, 72...correction circuit.
Claims (1)
、この基準信号発生器からの出力信号により通常
駆動パルス信号を出力する分周回路と、順方向修
正スイツチと、逆方向修正スイツチと、この両修
正スイツチのいずれか一方が操作されたことを検
出して前記修正用パルス信号を出力するとともに
前記分周回路の動作を停止させ、それ以外の時は
通常駆動パルス信号を出力する切換回路と、この
切換回路からのパルス信号の発生に対応して複数
の出力端より一定方向に出力信号の発生を移行す
るとともに前記逆方向修正スイツチの操作時のみ
その移行方向が反転する駆動回路と、この駆動回
路に接続されその出力信号の発生に応答して回転
駆動する多相モータと、この多相モータの回転に
よつて駆動する輪列及び指針と、 を有するアナログ時計において、 前記切替回路および駆動回路からの信号により
前記逆方向修正スイツチの操作が為されたことを
検知するとともに前記分周回路からの通常駆動パ
ルスの発生に応答して前記切換回路に設定数の修
正用パルス信号を駆動回斑に強制出力させる制御
信号を出力する補正回路を、設けたことを特徴と
するアナログ時計の修正回路。[Claims for Utility Model Registration] A reference signal generator that generates a correction pulse signal, a frequency divider circuit that outputs a normal drive pulse signal based on the output signal from the reference signal generator, a forward correction switch, and a reverse correction switch. A direction correction switch detects that either one of the two correction switches is operated and outputs the correction pulse signal and stops the operation of the frequency dividing circuit.Otherwise, the normal drive pulse signal is output. A switching circuit that outputs a pulse signal, and a switching circuit that shifts the output signal generation from a plurality of output terminals in a fixed direction in response to the generation of a pulse signal from this switching circuit, and the direction of the shift is reversed only when the reverse direction correction switch is operated. An analog clock comprising: a drive circuit, a polyphase motor that is connected to the drive circuit and rotates in response to the generation of an output signal from the drive circuit, and a wheel train and hands that are driven by the rotation of the polyphase motor. , detecting that the reverse direction correction switch has been operated by signals from the switching circuit and the driving circuit, and causing the switching circuit to correct the set number in response to the generation of the normal driving pulse from the frequency dividing circuit. 1. A correction circuit for an analog timepiece, comprising a correction circuit that outputs a control signal for forcing a drive pulse signal to be outputted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14623388U JPH0542387Y2 (en) | 1988-11-08 | 1988-11-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14623388U JPH0542387Y2 (en) | 1988-11-08 | 1988-11-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0267296U true JPH0267296U (en) | 1990-05-22 |
| JPH0542387Y2 JPH0542387Y2 (en) | 1993-10-26 |
Family
ID=31415531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14623388U Expired - Lifetime JPH0542387Y2 (en) | 1988-11-08 | 1988-11-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0542387Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5660093B2 (en) * | 2012-08-31 | 2015-01-28 | カシオ計算機株式会社 | Analog electronic clock |
-
1988
- 1988-11-08 JP JP14623388U patent/JPH0542387Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542387Y2 (en) | 1993-10-26 |
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