JPS6453620A - Flip-flop circuit - Google Patents
Flip-flop circuitInfo
- Publication number
- JPS6453620A JPS6453620A JP63132954A JP13295488A JPS6453620A JP S6453620 A JPS6453620 A JP S6453620A JP 63132954 A JP63132954 A JP 63132954A JP 13295488 A JP13295488 A JP 13295488A JP S6453620 A JPS6453620 A JP S6453620A
- Authority
- JP
- Japan
- Prior art keywords
- output
- inverter
- steps
- nand gate
- specified
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To obtain a low energy consumption at high speed action by minimizing the number of the steps of gates until the level of an output edge is specified in a presetting or clear type FF. CONSTITUTION:When resetting is applied to a master slave FF, a presetting input is '0', a clear input is '1', and therefore, the output of an inverter 1 is '1' and thus, the output of a NOR gate 2 is '0'. The output of an inverter 3 is '0', the output of an inverter 5 is also '0', and thus, an output Q is set to '1'. On the other hand, the output of the inverter 1 is '1', the output of an inverter 6 is '1', and therefore, an output Q of a NAND gate 32 is set to '0'. Thus, at the output Q side, the output level is specified by three steps of inverters 1 and 3 and a NAND gate 31 or three steps of the inverter 1, the NOR gate 2 and the NAND gate 31, and at the output Q side, the level is specified by two steps of the inverter 1 and the NAND gate 32, and therefore, the low energy consumption can be obtained at a high speed. This is also the same as when clearing is applied.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63132954A JPS6453620A (en) | 1988-05-31 | 1988-05-31 | Flip-flop circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63132954A JPS6453620A (en) | 1988-05-31 | 1988-05-31 | Flip-flop circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6453620A true JPS6453620A (en) | 1989-03-01 |
JPH0366845B2 JPH0366845B2 (en) | 1991-10-18 |
Family
ID=15093383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63132954A Granted JPS6453620A (en) | 1988-05-31 | 1988-05-31 | Flip-flop circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6453620A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0409465A2 (en) * | 1989-07-17 | 1991-01-23 | MITSUI TOATSU CHEMICALS, Inc. | Preparation process of polyimide film |
-
1988
- 1988-05-31 JP JP63132954A patent/JPS6453620A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0409465A2 (en) * | 1989-07-17 | 1991-01-23 | MITSUI TOATSU CHEMICALS, Inc. | Preparation process of polyimide film |
EP0409465B1 (en) * | 1989-07-17 | 1994-01-26 | MITSUI TOATSU CHEMICALS, Inc. | Preparation process of polyimide film |
Also Published As
Publication number | Publication date |
---|---|
JPH0366845B2 (en) | 1991-10-18 |
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