JPS6448298A - Rom circuit - Google Patents

Rom circuit

Info

Publication number
JPS6448298A
JPS6448298A JP20382787A JP20382787A JPS6448298A JP S6448298 A JPS6448298 A JP S6448298A JP 20382787 A JP20382787 A JP 20382787A JP 20382787 A JP20382787 A JP 20382787A JP S6448298 A JPS6448298 A JP S6448298A
Authority
JP
Japan
Prior art keywords
trs
drain
circuit
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20382787A
Other languages
Japanese (ja)
Inventor
Shigeki Morizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20382787A priority Critical patent/JPS6448298A/en
Publication of JPS6448298A publication Critical patent/JPS6448298A/en
Pending legal-status Critical Current

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  • Read Only Memory (AREA)

Abstract

PURPOSE:To obtain a low energy consumption ROM circuit by constituting the circuit of a P-shaped MOS transistor (TR) whose respective sources are connected to a voltage source, an N-shaped MOS transistor whose source is connected to a ground and an N-number of the N-shaped MOS TRs. CONSTITUTION:The titled circuit is composed of first and second TRs of a first polarity of which the respective source are connected to the first voltage source, a third TR of a second polarity whose source is connected to a second voltage source and the N-number of the TRs. The gate of the first TR is connected to the drain of the second TR and the gate of the second TR is connected to the drain of the first TR. Then, the gate of the third transistor is connected to a first control input terminal. The drain is connected to the drain of the first TR and the gates of the N-number of TRs of the second polarity are respectively connected to the N-number of input terminals. Then, the writing of the ROM is executed separately when the respective drains of the N-number TRs are connected to the drain of the second TR and when they are not connected. Thus, the ROM circuit of the low energy consumption can be realized.
JP20382787A 1987-08-17 1987-08-17 Rom circuit Pending JPS6448298A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20382787A JPS6448298A (en) 1987-08-17 1987-08-17 Rom circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20382787A JPS6448298A (en) 1987-08-17 1987-08-17 Rom circuit

Publications (1)

Publication Number Publication Date
JPS6448298A true JPS6448298A (en) 1989-02-22

Family

ID=16480366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20382787A Pending JPS6448298A (en) 1987-08-17 1987-08-17 Rom circuit

Country Status (1)

Country Link
JP (1) JPS6448298A (en)

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