JPS5754427A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS5754427A
JPS5754427A JP55130493A JP13049380A JPS5754427A JP S5754427 A JPS5754427 A JP S5754427A JP 55130493 A JP55130493 A JP 55130493A JP 13049380 A JP13049380 A JP 13049380A JP S5754427 A JPS5754427 A JP S5754427A
Authority
JP
Japan
Prior art keywords
circuit
signal
input signal
gate
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55130493A
Other languages
Japanese (ja)
Inventor
Hidetoshi Kosaka
Kuniharu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55130493A priority Critical patent/JPS5754427A/en
Publication of JPS5754427A publication Critical patent/JPS5754427A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To accept any input signal without requiring the change in externally mounted circuits, by setting or resetting FFs through an instruction. CONSTITUTION:A source electrode of P channel MOS transistors TRs 21, 22 is connected to an input terminal, the drain electrode of the TR21 is connected to a power supply -V, and a gate is connected to a true value output terminal Q of an FF circuit 28. The dran of the TR22 is connected to ground potential and the gate is connected to an inversion value output terminal Q' of the circuit 28. With this circuit constitution, when the potential is at L at the presence of an input signal and at H at no signal, the output Q of the circuit 28 is at H and the Q' is at L with instruction signals Inst A, B. Inversely, if H at input signal and L at no signal, the output Q of the circuit is at L and the Q' is at H with the signals Inst A, B.
JP55130493A 1980-09-19 1980-09-19 Input circuit Pending JPS5754427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55130493A JPS5754427A (en) 1980-09-19 1980-09-19 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55130493A JPS5754427A (en) 1980-09-19 1980-09-19 Input circuit

Publications (1)

Publication Number Publication Date
JPS5754427A true JPS5754427A (en) 1982-03-31

Family

ID=15035576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55130493A Pending JPS5754427A (en) 1980-09-19 1980-09-19 Input circuit

Country Status (1)

Country Link
JP (1) JPS5754427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113430U (en) * 1984-12-27 1986-07-17
JPS61131133U (en) * 1985-02-01 1986-08-16

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113430U (en) * 1984-12-27 1986-07-17
JPS61131133U (en) * 1985-02-01 1986-08-16
JPH0450658Y2 (en) * 1985-02-01 1992-11-30

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