JPS6447060A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6447060A
JPS6447060A JP20548187A JP20548187A JPS6447060A JP S6447060 A JPS6447060 A JP S6447060A JP 20548187 A JP20548187 A JP 20548187A JP 20548187 A JP20548187 A JP 20548187A JP S6447060 A JPS6447060 A JP S6447060A
Authority
JP
Japan
Prior art keywords
internal electrodes
row
bonding wire
80mum
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20548187A
Other languages
Japanese (ja)
Inventor
Kiyoshi Katsuraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20548187A priority Critical patent/JPS6447060A/en
Publication of JPS6447060A publication Critical patent/JPS6447060A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To make a bonding wire hard to be short-circuited by a method wherein first internal electrodes formed in a line in a vertical direction on the step higher than an IC chip mounting section by a step and second internal electrodes formed at the position higher than the first internal electrodes in level by 20-80mum are provided. CONSTITUTION:Internal electrodes 3 in the first row are equal to internal electrodes 2 in the second row in thickness and an alumina coated film 10 20-80mum in thickness is formed on a step on a ceramic substrate where the internal electrodes 2 in the second row are to be built before these internal electrodes 2 and 3 are printed on. Therefore, the internal electrodes in the second row are made to be substantially higher than the first row internal electrodes in level by 20-80mum, whereby a bonding wire 6 in the first row connecting the first row internal electrodes 3 with each connecting section of an IC chip is made to differ from a bonding wire 5, which connects the second row internal electrodes 2 with each connecting section of an IC chip 7, in level, so that the short-circuit between the first row bonding wire 6 and the second row bonding wire 5 is prevented from taking place.
JP20548187A 1987-08-18 1987-08-18 Semiconductor device Pending JPS6447060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20548187A JPS6447060A (en) 1987-08-18 1987-08-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20548187A JPS6447060A (en) 1987-08-18 1987-08-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6447060A true JPS6447060A (en) 1989-02-21

Family

ID=16507568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20548187A Pending JPS6447060A (en) 1987-08-18 1987-08-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6447060A (en)

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